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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Verification

"Day 0" of CDNLive San Jose 2008

Quick report from CDNLive Day 0 (I've labeled it that since this initial day was…

• 1 min read
CDNLive San Jose 2008 , MDV techtorial , System Verification

Verification

CDNLive SJ - system design and verification - don't miss it

If you are a system validation/verification engineer, an architect, a power engineer…

• 1 min read
Low Power , power engineer , system validation/verification engineer , embedded SW engineer , architect

System, PCB, & Package Design 

CDNLive! 2008 - San Jose: Day 1 ... from the Techtorials!

From the floor of CDNLive! 2008 - San Jose The first day, is always considered the…

• 1 min read
PCB Layout and routing , CDNLive , DEHDL , SPB16.2 , Design Entry HDL , ASA , Allegro System Architect (ASA) , Front-end PCB design , PCB design , CDNLive! , Allegro PCB Editor , ConceptHDL

Digital Design

Need for dynamic IR drop analysis at floor and power planning stages?

Here is a question for all the power grid designers out there: Do you see the need…

• 1 min read
dynamic rail analysis , Early Rail Analysis , Cadence Encounter Power System , Digital Implementation

Analog/Custom Design

CDNLive Techtorials: Everything you wanted to know about Virtuoso

Hey folks, if you are coming to the CDNLive conference, we have a lot of great "techtorials…

• less than a min read
RF design , CDNLive Techtorials , custom design technology

Verification

See you at CDNLive San Jose next week

FYI, Mike Stellfox and I will be at CDNLive San Jose next week. In addition to reporting…

• less than a min read
Functional Verification , OVM , ISX (Incisive Software Extensions) , IES

Verification

Chip Level Verification with Processors

Today, I will discuss some alternatives for chip-level verification with designs…

• 6 min read
verification strategy , Functional Verification , ISX , ARM , FPGA: DMA

Digital Design

Effectively communicating Low-Power and Power-Efficient Design knowledge

For those of you interested in the Power space I recently had an article published…

• less than a min read
Low-Power , Power-Efficient Design , Logic Design , Digital Implementation

RF Engineering

Tip of the Week: When should I use the pss/qpss Harmonic Balance vs. Shooting Newton…

Shooting Newton (shooting) and harmonic balance (HB) are complementary technologies…

• less than a min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design , Circuit Design

Digital Design

Demo: Interactive Floorplanning in SoC-Encounter

In this demonstration, we'll show how to perform the following actions: Resize a…

• less than a min read
SoC-Encounter , screencast , Rectilinear Cut , Floorplanning and Prototyping

System, PCB, & Package Design 

What's good about memristors? Who is planning on using them?

I recently read an interesting article in the August 18, 2008 Electronic Engineering…

• 1 min read
memristors , PCB design , Electronic Engineering Times

Verification

The Road to Better Software Verification

It seems the debate over the benefits of better software verification is still alive…

• 5 min read
Intel , Specman , System Design and Verification , Frank Schirrmeister

Digital Design

Demo: How To Make Multiple Edits with "Apply All" in SoC-Encounter

Today, I'm starting what I hope will be a series of screencasts where I demonstrate…

• less than a min read
SoC-Encounter , screencast , Digital Implementation , Apply All , Attribute Editor

RF Engineering

Tip of the Week: Guidelines for simulating oscillators - phase noise simulations

When simulating oscillators, it is important to choose the correct simulator engine…

• 2 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator XL , Spectre , RF design

Verification

ESL: The state of the industry and what’s next?

While ESL continues to remain in its infancy, there are signs within the industry…

• less than a min read
System Design and Verification , ASIC/ASSP , advanced process nodes , ESL

System, PCB, & Package Design 

Analog/RF chip designers don't care about the Package?

So I have an observation that I would your thoughts/input on. On several occassions…

• less than a min read
Analog and RF SiP design , Analog chip design , IC Packaging & SiP design , Virtuoso , IC Package Physical layout and co-design , design chain

Verification

Experiences on Marketing a Verification Library

Inspired by JL Gray of the blog "Cool Verification" who stated, in this post: "I…

• 2 min read

System, PCB, & Package Design 

How stable is your IC Package's PDN?

There are three goals for a power a delivery network (PDN): sufficiency, efficiency…

• less than a min read
PDN , CDNLive , SPB , SPB16.2 , SerDes , SSN , DDR3

Verification

Embedded Systems Conference Boston 2008

Friday is that last day to get the Early Bird price for the Embedded Systems Conference…

• 1 min read
System Design and Verification , Coverage Driven Verification for Embedded Software , Embedded Systems Conference 2008 , debugging , Jason Andrews , verification
CDNS - Fix Layout Hompage