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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

Verification

Coverage Maximization

Searching for “automatic coverage maximization” results with ~16 million hits. Alas…

• 4 min read
Specman , coverage , Functional Verification , Testbench simulation , Coverage-Driven Verification , CDV , e , e language , Funcional Verification , team specman , specman elite , verification

Breakfast Bytes

Wearables: Growing at 38% CAGR?

At what has now become the Linley Mobile and Wearables Conference, Linley pointed…

• 3 min read
smartwatch , quaqlcomm , Linley , wearables , smart watch , mobile

SoC and IP

MIPI DevCon 2016 – Mobile and Beyond

MIPI DevCon 2016 – Mobile and Beyond The word “beyond” may bring up thoughts of…

• 6 min read
MIPI Alliance , ADAS

Whiteboard Wednesdays

Whiteboard Wednesdays - Radar Signal Processing Optimized for the Tensilica Fusion…

In this week's Whiteboard Wednesday video, Pushkar Patwardhan discusses the advantages…

• less than a min read
Whiteboard Wednesdays , IP , radar signal processing , Tensilica

Breakfast Bytes

CDNLive India Keynote

The keynote at CDNLive Bengaluru was given by Michal Siwiński. Since day 1 of CDNLive…

• 2 min read
CDNLive India , SDE , system design enablement , Breakfast Bytes

SoC and IP

Less is More With MIPI I3C

There is little doubt that Internet of Things has become the next big thing in business…

• 1 min read
peripherals , IoT , MIPI , i2c , sensors , hdr , I3C , sensewire , hub

Breakfast Bytes

SEMICON Best of the West: Coventor

SEMICON West runs a sort of award program called Best of the West. Companies submit…

• 3 min read
semicon west , semi , Coventor , semulator3d , best of the west

Breakfast Bytes

Perspec Modeling

The post A Perspective on Perspec earlier this week introduced the idea of Perspec…

• 3 min read
Perspec , perspec system verifier , UML , system verilog

Analog/Custom Design

High-Sigma Showdown: Which Method is Better?

The adoption and usage of advanced node technology (16nm and below) has been extraordinary…

• 3 min read
variation tsmc hsmc sss sampling high sigma

Breakfast Bytes

What's for Breakfast? August 22nd

http://youtu.be/ZkZQAW6Gl7M Monday: At SEMICON West the winner of the "Best of…

• less than a min read
provisioning , security , Intel , CDNLive India , linley group , shockley , wearables , Qualcomm , Fairchild , a16z , cdnlive bengaluru , Coventor , mobile , Silicon Valley

Breakfast Bytes

Palladium and Protium Platforms, the Hardware Twins

The Palladium Z1 is an enterprise-level emulation system. If you don't already know…

• 4 min read
palladium z1 , Protium , Palladium , Emulation , FPGA prototyping

Breakfast Bytes

Omnia Simulation in Tres Partes Divisa Est

"Omnia Gallia in tres partes divisa est" were the opening words to Julius Caesar…

• 3 min read
verilog-xl , Verilog , rocketick , rocketsim , simulation

Whiteboard Wednesdays

Whiteboard Wednesdays - Tensilica Fusion G3 DSP Features and Benefits

In this week's Whiteboard Wednesdays video, Paul Garden provides more details on…

• less than a min read
Whiteboard Wednesdays , IP , Tensilica , Tensilica Fusion G3

Verification

10 New Protocols to Design and Integrate Your SoC in Record Time

This month we released 10 new Verification IP for leading-edge protocols! Did I say…

• 1 min read
SPI NAND , Verification IP , VIP , MIPI , DisplayPort , USB , DSI , octal spi , Ethernet , Tensilica , design , Type-C , and Verification IP , USB UFS

Breakfast Bytes

A Perspective on Perspec System Verifier

Today we have UVM, the universal verification methodology. This is great for verifying…

• 4 min read
Perspec , perspec system verifier , cache coherency , ARM , power

SoC and IP

Building the Cars of the Future

The big buzz in the automotive industry lately is autonomous driving vehicles. Companies…

• 3 min read
Verification IP , VIP , Automotive Ethernet , CAN , automotive electronics , Ethernet , Design IP and Verification IP , Lin

Breakfast Bytes

What's for Breakfast? August 15th

It's verification week this week, with 5 posts about various aspects of Cadence's…

• 1 min read
Breakfast Bytes

Breakfast Bytes

Verification Technology Update

At CDNLive in Bengaluru last week, Michal Siwiński gave a technology update on verification…

• 4 min read
Perspec , Protium , VIP , Palladium , Incisive , Indago , JasperGold , Breakfast Bytes , vManager , verification

Breakfast Bytes

5G, Coming Soon to a Phone Near You

At the Linley Mobile Conference recently, the morning after Linley's keynote was…

• 3 min read
5G , Linley , simultaneous connectivity , mobile , Breakfast Bytes
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