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Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI
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Blog - Post List

Latest blogs

Corporate News

Introducing Fem.AI: Reshaping the Tech/AI Workforce for a More Equitable Future

The Cadence Giving Foundation was founded in 2022 to support critical needs in communities…

• 2 min read
Cadence Giving Foundation , featured , Cadence Cares , Fem.AI , AI , Women in Technology

System, PCB, & Package Design 

DesignCon Best Paper 2024: Addressing Challenges in PDN Design

Explore Impacts of Finite Interconnect Impedance on PDN Characterization Over…

• 1 min read
featured , DesignCon , PDN , signal integrity analysis , Signal Integrity , PDN Analysis , Sigrity

Corporate News

Cadence Tensilica HiFi 5 DSPs Used in NXP’s Next-Gen Audio DSP Family

In a significant achievement for the automotive industry, Cadence's Tensilica HiFi…

• 2 min read
Automotive , featured , Tensilica , AI/ML , technology

Digital Design

The Best Way to Learn – Cadence Cerebrus AI-Driven Design Implementation

The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning…

• 2 min read
digital badge , live training , cerebrus , Cadence training , cadence learning and support

Digital Design

Conformal ECO Designer

Conformal ECO Designer enables you to implement RTL engineering change orders (ECOs…

FormerMember • 1 min read
Conformal ECO Designer , conformal , RTL design

Verification

Training Insights – Palladium Emulation Course for Beginner and Advanced Users

The Cadence Palladium Emulation Platform is a hardware system that implements the…

• 2 min read
digital badge , live training , blended training , Palladium , Training Insights , online training

Verification

Flow Control Credit Updates in PCIe 6.1 ECN

As technology continues to evolve at a rapid pace, the importance of robust and efficient…

• 3 min read
Verification IP , PCIExpress , PCIe , pcie gen6 , PCIe 6.0 , verification

Life at Cadence

From Student Challenge to Professional Journey: An Intern’s Story at Cadence

At Cadence, we pride ourselves on fostering a culture of innovation and excellence…

• 3 min read
CFD , Insights on Culture , Cadence Culture , Computational Fluid Dynamics , Fidelity CFD

Verification

Use Verisium SimAI to Accelerate Verification Closure with Big Compute Savings

Verisium SimAI App harnesses the power of machine learning technology with the Cadence…

• 3 min read
Functional Verification , verisium , machine learning , SimAI , AI

Corporate News

Kalray Is Pioneering DPU Development

A leading provider of hardware and software solutions for data-centric applications…

• 1 min read
cerebrus , designed with cadence , Innovus Implementation

Verification

Maximizing Display Performance with Display Stream Compression (DSC)

Display Stream Compression (DSC) is a lossless or near-lossless image compression…

• 2 min read
resolution , DisplayPort , Display Stream Compression , lossless

Verification

Unlocking the Secrets of Next-Gen Verification

In the world of electronic design automation (EDA), verification is the glue that…

• 4 min read
Functional Verification , verisium , SimAI , Verisium Debug , xcelium , AI/ML , verification

Verification

Verisium SimAI: Maximizing Coverage, Minimizing Bugs, Unlocking Peak Throughput

Navigating the complexities of maximizing efficiency in random testing for designs…

• 2 min read
IP , cadence , verisium , SimAI

Corporate News

GlobalFoundries and Cadence Collaborate to Enable Design of the Digital World

The collaboration between GlobalFoundries (GF) and Cadence represents a powerful…

• 3 min read
featured , gf , GlobalFoundries , AI

Data Center

Why Does a Data Center Need a Digital Twin?

Recent advances in data center management demonstrate the limitations of traditional…

• 1 min read
featured , futurefacilities , AI data center , data center , digital twin , data center digital twin , AI factory , data center software , cooling

Digital Design

Unlocking the Concepts of IEEE 1801 Standard for Efficient Power Management

Power efficiency is a critical factor in the fast-evolving world of semiconductor…

• 4 min read
Low Power , IEEE 1801 , training , training bytes , UPF , Power Analysis

Computational Fluid Dynamics

Redefining Speed and Efficiency in Automotive CFD Workflows with Fidelity CFD

Automotive geometries tend to be intricate, often requiring “cleaning” before a final…

• 4 min read
Automotive , Computational Fluid Dynamics , Fidelity CFD , simulation software , Mesh Generation , preprocessing

Corporate News

Verisium SimAI: SoC Verification with Unprecedented Coverage Maximization

As hardware complexity increases, the limitations of traditional design verification…

• 1 min read
coverage , bugs , verisium , SimAI , xcelium , Regression

PCB解析／ICパッケージ解析

System Analysis Knowledge Bytes: PDNシミュレーションにおけるVRMモデリングの重要性

System Analysis Knowledge Bytes ブログシリーズでは、Cadenceが提供するシステム解析ツールの機能と可能性について説明しています…

• 1 min read
PDN , Power Integrity , Cadence Online Support , Sigrity OptimizePI , Signal Integrity , japanese blog , RAKs , Voltage Regulator Modules , VRMs
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