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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

Reduce Flip-Chip Design Time with Cadence Advanced Package Router (APR) for 16.6…

Perhaps the most time-consuming aspect to designing the package substrate for a large…

• 1 min read
IC Package , IC Packaging , Digital SiP design , Advanced Package Router , 16.6 , IC Packaging and SiP , APR , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , IC Package Physical layout and co-design

System, PCB, & Package Design 

Customer Support Recommended – Regulation Loop Design Using Allegro AMS Simulator…

Feedback regulation loops are widely used by power electronic designers. It is one…

• 3 min read
SPB16.3 , Allegro 16.6 , customer support , AMS simulator , closed loop design , 16.6 , Allegro 16.3 , Support , Allegro AMS , Allegro 16.5 , PSPICE , Appnotes , loop design , regulation loops , Appnote , feedback regulation loops , "PCB design" , open loop design , PCB design , 16.5 , AMS simulation , SPB16.5 , application note , Schematic

System, PCB, & Package Design 

What's Good About Allegro Package Designer (APD) Bond Wire "Text In?" You’ll Need…

Cadence IC Packaging tools today provide a spreadsheet-based import mechanism for…

• 2 min read
PCB , IC Packaging , Allegro 16.6 , cadence , 16.6 , APD , Wirebond , Allegro Package Designer , design , bond wires , Grzenia , die abstract , wire bond , Allegro

Analog/Custom Design

Virtuosity: 10 Things I Learned in February By Browsing Cadence Online Support

February was a big month for RAKs (Rapid Adoption Kits)! If you haven't checked out…

• 3 min read
AMS , APS , Virtuoso Advanced Node , Virtuoso IC6.1.5 , IC 6.1 , Rapid Adoption Kit , Analog Simulation , Advanced Node , IC615 , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , variability , Spectre , Analog Design Environment , ADE-XL , Virtuosity , Custom IC Design , RAKs , Virtuoso Layout Suite GXL

Verification

What to See at the DATE Conference: High-Level Synthesis

The DATE (Design Automation and Test in Europe) Conference is next week (March 18…

• 1 min read
High-Level Synthesis , DATE , Alex Kondratyev , C-to-Silicon Compiler , HLS , system-level , ESL , QoR , System Design and Verification

Verification

Specman: Getting Source Information on Macros

When you write a define-as or define-as-computed e macro, you sometimes need the…

• 2 min read
AF , Specman , Functional Verification , source information on macros , e language , team specman , macros , messages

Verification

DVCon 2013: Functional Verification Is EDA’s “Killer App”

With another year of record attendance, DVCon has again proven that a functional…

• 3 min read
Joe Hupcey III , Specman , methodology , Team Verify , DVCon 2013 , metric driven verification (MDV) , Functional Verification , Formal Analysis , UVM e , Specman e , formal , formal apps , Richard Goering , e code , e , e language , DVcon , apps , papers , metrics , verification

Digital Design

CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance…

Implementing SoCs with embedded processors at advanced nodes has become increasingly…

• 5 min read
ARMv8 , EDI , Low Power , Cortex-A15 , CDNLive , Cortex-A57 , Cortex-A7 , RC-Physical , NVIDIA , Avago , SoC , ccopt , digital , GigaOpt , Digital Implementation , Encounter Digital Implementation , AppliedMicro , high performance , CDNLive Silicon Valley , ARM , CDNLive! Cadence

Verification

System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and…

Ever since switching from being a hardware/software chip developer to being an enabler…

• 4 min read
AVIP , Intel , Verification IP , RPP , Low Power , Verification Computing Platform , Virtual System Platform , Fast Models , PXP , CDNLive , cadence , Acceleration , Teledyne LeCroy FPGA Based Prototyping , System to Silicon Verification , AMD , Dynamic Power Analysis , System Design and Verification , System Development Suite , Samsung , embedded software , VSP , Incisive , Palladium XP , Emulation , Imperas , Freescael , Bluespec , CDNLive! , ARM , Schirrmeister , Accelerated Verification IP , low power optimization , VCP

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Place Replicate Text Support? Check Out 16.6

The Allegro PCB Editor Place Replicate application now supports the processing of…

• 1 min read
PCB , PCB Layout and routing , place replicate text support , Allegro GUI , Allegro 16.6 , 16.6 , Placement Edit , place replicate , PCB Editor , Layout , "PCB design" , PCB design , Grzenia , Allegro PCB Editor , Allegro

System, PCB, & Package Design 

Remove Die Stack Layers from NC Drill Outputs using Cadence 16.6 SiP and APD IC Packaging…

As we continue with our series on improvements to the manufacturing and documentation…

• 3 min read
stacked dies , SiP , IC Package , IC Packaging , packaging , Digital SiP design , 16.6 , die stack layers , IC Packaging and SiP , APD , IC Packaging & SiP design , Allegro Package Designer , NC drill outputs , APD 16.6 , SiP Layout , Physical layout and co-design

Verification

Securing Invisible Things … or “Why Denial Works!”

The opening keynote of the Embedded World conference in Germany left me with chills…

• 4 min read
security , Automotive , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , Vulnerabilities , cadence , Acceleration , Functional Verification , Safety , McClure , System Design and Verification , System Development Suite , Driver Assist , embedded software , Palladium XP , Emulation , DVcon , Testing , Cylance , ADAS , ARM , Error Injection , Embedded World , Schirrmeister , Hacking Exposed , verification

System, PCB, & Package Design 

What's Good About Allegro AMS New Advanced Options? They’re in the 16.6 Release!

The Allegro AMS Simulator (analog/mixed-signal) 16.6 release adds several enhancements…

• 2 min read
AMS , Allegro 16.6 , advanced options , AMS simulator , 16.6 , MS simulation , Allegro AMS , PSPICE , SPB , PCB design , Grzenia , analog/mixed signal

Analog/Custom Design

"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification

We are seeing a huge trend -- the mobile revolution is changing the way we go about…

• 4 min read
AMS , DVCon 2013 , CDNLive 2013 , SV-DC , Verilog-AMS , analog , Incisive , Mixed-Signal , smart devices , analog behavioral models , analog/mixed-signal , Virtuoso , Internet of Things , RNM , Verilog AMS , mixed signal , SenseAware , wreal , Virtuoso environment , Schematic Model Generator , mixed-signal verification

Verification

Application Specific System-Design and Verification at Embedded World and DVCon

This week (February 25th 2013) is a busy one for system development and the Cadence…

• 3 min read
Nuremberg , virtual platforms , applications , virtual prototypes , System Design and Verification , application-specific , Mobile World Congress , System Development Suite , embedded software , automotive electronics , Internet of Things , software , DVcon , apps , software development , hardware/software , embedded systems , Embedded World , Schirrmeister

Verification

Embedded World 2013: Virtual Platforms Connected to Everything

Sometimes it is hard to explain why certain ideas take off and why others don’t.…

• 3 min read
virtual prototyping , RPP , Virtual System Platform , virtual platforms , embedded world conference , embedded software , VSP , Palladium XP , Emulation , system design , Rapid Prototyping Platform , System Design & Verification , Embedded World , linux , simulation

Digital Design

Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard…

In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script…

• 4 min read
power-grid views , Low Power , rail analysis , current density , LEF , EPS , standard cells , Digital Implementation , qrc , Power Analysis , signoff , EM , IR drop , five minute tutorial , encounter power system , power

Verification

What the 787 Dreamliner Can Teach Us About SoC design

The commercial aircraft industry is at a stage where it innovates at a much slower…

• 6 min read
Dreamliner , Boeing , Apple , 787 Dreamliner , TLM , fire , 787 , C-to-Silcon , Harvard Business Review , SoC , IP assembly , system design , SoC design , Apple A6 , SystemC , outsourcing , iPhone , Jay-Z , System Design and Verification

Verification

Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb…

TUTORIAL : Fast Track Your UVM Debug Productivity with Simulation and Acceleration…

• 1 min read
SystemVerilog , Specman/e , AVS , metric driven verification (MDV) , debug , Functional Verification , Debug Performance , debug tutorial , Incisive Debug Analyzer , Mixed Signal Verification , DVcon , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , IES-XL
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