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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

SoC and IP

Chemical vapor deposition creates improved material for PCM (phase-change memory…

Yesterday, semiconductor materials manufacturing specialist ATMI and Ovonics, the…

• less than a min read

SoC and IP

Commodore and its iconic all-in-one computers resurrected with new guts, including…

Everyone familiar with the arc of personal computers knows Commodore. The calculator…

• 1 min read

Verification

Join Us at FMCAD October 20-23

Are you deeply interested in formal and assertion-based verification technology?…

• less than a min read
Alok Jain , ABV , Functional Verification , Formal Analysis , formal , FMCAD , IEV , IFV

System, PCB, & Package Design 

What's Good About AMS Simulator New Design Templates? They’re in the SPB16.3 Release

What's Good About AMS Simulator New Design Templates? They're in the SPB16.3 Release…

• 1 min read
SPB16.3 , AMS , AMS simulator , SPB 16.3 , PSPICE , AMS simulation , Design Entry , Schematic

Verification

All I Really Need to Know About MDV I Learned From Hollywood - Part 2

My last blog entry began a series using quotes from Hollywood movies to illustrate…

• 2 min read
vPlan , verification planning , Verification IP modeling , metric-driven verification , MDV

SoC and IP

HP’s memristor finds a commercial semiconductor vendor: Hynix

The rumor at the recent Flash Memory Summit held earlier this month was that HP was…

• less than a min read

SoC and IP

Toshiba 24nm, 64-Gbit NAND Flash: Just a silly nanometer shorter

Toshiba announced today that it has initiated mass production of NAND Flash memories…

• less than a min read

SoC and IP

17 SSDs reviewed by Tom’s Hardware

We’re still at the stage where there can be appreciable differences in the performance…

• 1 min read

SoC and IP

Huawei talks Smart Memory at Hot Chips 22: “The only practical solution”

Last week saw the 22nd Hot Chips conference, held at held Stanford University, and…

• 3 min read

SoC and IP

A non-exhaustive list of 150 SSD vendors

A recent check of the Yahoo! Finance boards showed some skepticism about my previous…

• 1 min read

SoC and IP

PCM (now with carbon nanotubes!) programming current drops two orders of magnitu…

A fascinating Masters thesis written by Feng Xiong details the fabrication and testing…

• 1 min read

SoC and IP

Seagate and Samsung to jointly develop enterprise-class SSD controller -- a little…

A bit more than a week ago, HDD leader Seagate and NAND Flash leader Samsung jointly…

• 1 min read

Verification

All I Really Need to Know About MDV I Learned From Hollywood - Part 1

True story: this series of blog posts is inspired by a dream. I recently gave a presentation…

• 3 min read
vPlan , verification planning , Verification IP modeling , metric-driven verification , MDV

SoC and IP

8 key takeaways for system design teams from the Flash Memory Summit

Cadence’s Senior Manager of Technical Communications and a longtime EDA observer…

• less than a min read

Analog/Custom Design

Things You Didn't Know About Virtuoso: Outputs Setup in ADE XL

Continuing on our exploration of ADE XL (see here and here for previous articles…

• 5 min read
IC 6.1 , Analog Simulation , analog , ADE , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , IC 6.1.4 , Custom IC Design

System, PCB, & Package Design 

What's Good About Capture Objects Look and Feel? You Can Change Them in SPB16.3!

The SPB16.3 release of Allegro Design Entry CIS (known as Capture) has some cool…

• 2 min read
"capture CIS" , SPB16.3 , Allegro Design Entry , Capture CIS' , Design Entry CIS , OrCAD Capture , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , SPB , design , Design Entry , PCB Capture , Schematic

SoC and IP

Kingston DDR3 RAM cracks 3Gtransfers/sec barrier, achieves 3.068 Gtransfers/sec amid…

Mix liquid nitrogen and Kingston’s HyperX DDR3-2333 SDRAM modules and you get 3068…

• 1 min read

Digital Design

CDNLive! Silicon Valley Abstract Deadline Extended 1 Week

The deadline for submitting abstracts to CDNLive! Silicion Valley 2010 has been extended…

• less than a min read
CDNLive!

Verification

System Realization Webinars Start Sept 8th

Starting September 8th Cadence will be hosting a series of webinars about various…

• 2 min read
TLM , webinars , system realization , Calypto , Imperas , CircuitSutra , XtremeEDA , ESL
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