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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Latest blogs

Verification

Portable Design Names Cadence Incisive Palladium Dynamic Power Analysis its September…

In his article in Portable Design, John Donovan wrote: Palladium Dynamic Power Analysis…

• less than a min read
Portable Design , System Design and Verification , Palladium

Verification

Welcome Sharath Siddappa From Rambus, You Are The 5000th OVM World Registrant!

Welcome Sharath Siddappa, the 5000th OVM World registrant! In only 10 months, the…

• 1 min read
SystemVerilog , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , eRM , OVMWorld

Verification

OVM - The "O" Means Opportunity

A few months back I blogged that OVM was " Open for Business ". A nice play on words…

• 1 min read
Simantis , eclipse , KPIT , Functional Verification , IBM , Cadence VIP portfolio , OVM , Doulos

Verification

Report From the Advanced Verification Techtorial in San Jose Tuesday 10/28

I'm excited to report that Tuesday's techtorial, covering a range of topics underneath…

• 1 min read
Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , techtorial

Verification

The Power of Cadence System Power Flow vs. Viewing from the Top

I feel that I must respond to the following blog published by Frank Schirrmeister…

• 6 min read
Incyte Chip , System Design and Verification , Incisive Enterprise Simulator , Palladium , power engineer , C-to-Silicon , Power Analysis , Frank Schirrmeister

Verification

ESC Boston: Day 2

This morning before heading to ESC it dawned on me that the park across the street…

• 4 min read
System Design and Verification , ESC , ISX , Coverage Driven Verification

Analog/Custom Design

Video Demo: ViVA-XL - Fast Waveform Viewing

It’s happened to each of us at some point in time. Your long simulation is finally…

• less than a min read
ViVa-XL , MMSIM , Simulators , Custom IC Design , Fast Waveform Viewing

System, PCB, & Package Design 

What's Good About Directive Locking?

Do you wish you could lock specific aspects of a DEHDL design content? Do you need…

• 5 min read
CPM Directive Control , DEHDL , Directive Lockhing , PCB design , SPB16.01

Verification

Virtualization Taxonomy

I arrived safe and sound at the Embedded Systems Conference in Boston today. It's…

• 2 min read
VM ware , virtualization , taxonomy , real-time systems , Embedded Systems Conference , System Design and Verification , ESC

Verification

OVM Momentum and Interoperability

The question of how to integrate legacy VMM VIP into OVM verification environments…

• 1 min read
OVM Professionals Network , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , VIP , Verification IP modeling

Verification

Verification Techtorial in San Jose next Tuesday 10/28

Apologies for the shameless promotion, but I can't resist touting an event I'm producing…

• less than a min read
Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , techtorial

Verification

Formal Moment Of Zen

Most of my experience in functional verification prior to my dabbling in FPV was…

• 3 min read
OVL , FPV , Functional Verification , Formal Analysis , SCV , SVA , FIFO , PSL , Simulation acceleration , SystemC

System, PCB, & Package Design 

Need some stability in your Package Power?

It is not too late to sign up for the Package Power Integrity webinar that will be…

• less than a min read
PDN , IC Packaging & SiP design , SPB16.2 , SSN

Verification

Is Host-Code Execution History?

Before getting into the details of today's topic I'm happy to report a brand new…

• 5 min read
Cisco , System Design and Verification , MIPS , Palladium , Sun , Verilog , OVP , ARM , Virtutech , QEMU

Digital Design

Getting Started with dbGet

If you've been checking out the other blogs here in the Digital Implementation community…

• 2 min read
database access , SoC-Encounter , dbGet , dbSet

Verification

Top 5 Stumbling Blocks In FPV Adoption

My first post served as a context for this blog. It also telegraphed my intention…

• 5 min read
verification strategy , Verification methodology , Functional Verification , Formal Analysis , Model-checking , Testbench simulation , Coverage-Driven Verification

Verification

More on today's Verification IP portfolio expansion news

Today's announcement on our expanding Verification IP (VIP) portfolio inspired me…

• less than a min read
Functional Verification , Verification IP modeling , multi-language

Digital Design

An Interview with Global Timing Debug Architect Thad McCracken

So who is Thad McCracken and why should you be interesting in reading this blog entry…

• 8 min read
SoC-Encounter , Ostrich , Global Timing Debug

Verification

Getting more value from the OVM using Metric-Driven Verification - Part II

In my last post , I talked about how OVM is a methodology for building automated…

• 1 min read
metric driven verification (MDV) , Functional Verification , OVM , ARM , Incisive Enterprise Simulator (IES)
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