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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Things You Didn't Know About Virtuoso: Customizing the Library Manager

I've told you in previous postings about some new features in Virtuoso IC6.1 which…

• 3 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

Customer Questions About TLM-driven Design and Verification

In the latest blog published by Ron Wilson there were two questions about our TLM…

• 1 min read
System Design and Verification , TLM 2.0 , System C , C-to-Silicon , high level synthesis

Verification

DAC 2009 News: Specman 9.2 Highlights + Beta Program Invitation

Specmaniacs, With the start of DAC 2009, Team Specman is excited to finally be able…

• 1 min read
DAC , IntelliGen , Specman , Functional Verification , simvision , OVM e , e , SystemC , IES-XL

SoC and IP

Rethinking SSDs?

NAND Flash's SSD Vision: Wholesale replacement of HDDs by SSDs in the huge market…

• 7 min read

Verification

FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364

The mighty FSM – you first learned it when you were a young pup at University (some…

• 1 min read
SystemVerilog , debug , Functional Verification , simvision , Verilog , IES

Digital Design

Reducing Risk and Improving Productivity with the Cadence InCyte Chip Estimator and…

I'm looking forward to heading out to San Francisco next week for the 46th Design…

• 1 min read
DAC , Digital Implementation , Cadence InCyte Chip Estimator , Encounter Digital Implementation System 8.1

Verification

DAC '09 for the Specmaniac

The following are the "must see" items for Specmaniacs lucky enough to get travel…

• 3 min read
DAC , Specman , Functional Verification , OVM e , e , Mike Stellfox , Jason Andrews

System, PCB, & Package Design 

What's Good About Allegro's Placement Application Mode? - Look to SPB16.2 and See

In prior releases, Allegro PCB Editor does not provide the user the ability to place…

• 5 min read
Allegro 16.2 , PCB Editor , PCB design

Verification

At DAC Next Week

Yours truly will be at the big show next week, and I hope that all of you in the…

• 1 min read
DAC , Specman , Functional Verification , OVM , OVM e , DVcon

Verification

Simulation of Voltage Scaling for Dynamic Power Reduction

Some background info: In a previous blog , I introduced: DVFS (Dynamic Voltage…

• 2 min read
Low Power , Real Value Modeling , Functional Verification , Advanced Node , wreals , Mixed-Signal , Signal Integrity , verification

Verification

It's DAC Time Again!

By now, you've probably seen that Cadence is participating quite heavily in DAC this…

• 2 min read
DAC , Functional Verification , verification

Verification

Specman And The Cadence ESL+TLM News

Recently our colleagues on Team ESL announced a new TLM-Driven Design and Verification…

• 2 min read
IEEE 1647 , DAC , Specman , TLM , Verification methodology , Functional Verification , simvision , OVM e , e , Aspect Oriented Programming , eRM , Incisive Enterprise Simulator (IES) , ESL , AOP , IES-XL

Analog/Custom Design

DesignCon 2010 Call for Papers

Hello, As a member of the technical committee and as the chair member for the Analog…

• less than a min read
DesignCon , Advanced Node , Mixed-Signal , RF design , mixed signal , Custom IC Design

Verification

What is Next for SystemC?

Let your voice be heard at the North American SystemC Users Group interactive Town…

• 1 min read
TLM , System Design and Verification , OSCI , SystemC , high level synthesis , HLS

Verification

The Scoop on Tracking & Validating Formal Assumptions – You Don’t Need to Assume

" Tackling formal assumptions through verification planning " is a recent article…

• less than a min read
funtional verification , ABV , Verification methodology , metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , Incisive , Enterprise Manager , Enterprise Planner , coverage driven verification (CDV) , Functional Verificatioa , verification

Verification

North American SystemC User's Group Co-Located at DAC 2009

We've been hearing about SystemC for a while. It's a great language! What's it great…

• less than a min read
OSCI , Analysis , SystemC , NASCUG , System Design and Verification

Verification

Write Right OVM Verification Components

The OVM provides the most comprehensive reuse if you follow the methodology it prescribes…

• 4 min read
SystemVerilog , OVM ML , OVM e , OVM SV , OVMWorld

Analog/Custom Design

Things You Didn't Know About Virtuoso: Search Assistant

People say I have strong google-fu . Whether it's finding information on a homework…

• 3 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

SoC and IP

NAND Forward Price Drops will Slow Significantly

Author's Note and Errata: There were some errors in the forward NAND pricing in the…

• 9 min read
CDNS - Fix Layout Hompage