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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About Allegro Measure, Grids and Formulas? See For Yourself in SPB16

This week, I’m tossing together a mix of a few new SPB16.3 Allegro PCB Editor features…

• 2 min read
grids , PCB , PCB Layout and routing , Allegro 16.3 , SPB 16.3 , SPB , formulas , PCB Editor , High-Density Interconnect , Layout , via , design , PCB design , Allegro PCB Editor , Cline change , HDI , microvia , Allegro

Analog/Custom Design

Advanced Mixed-Signal Designs Demand a Unified Methodology

Mobile, automotive, consumer and medical applications require the productive realization…

• 4 min read
conformal , RF , mixed-signal seminars , Low Power , CPF , abstraction , analog , ECOs , Mixed-Signal , Convergence , intent , Silicon Realization , mixed signal , signoff , SoCs

Verification

De-Mystifying SystemC: What is TLM?

In my last post I briefly mentioned that when designing hardware with SystemC, you…

• 2 min read
High-Level Synthesis , Registers , TLM , Models , C to Silicon , transaction level modeling , SystemC , Modeling , System Design and Verification

System, PCB, & Package Design 

Team Allegro Continues Demonstration of New PDN Analysis Technology at DesignCon…

Today at DesignCon, drop by the Cadence booth to see TeamAllegro continue the demonstration…

• 1 min read
PCB SI , PCB , PCB PI , PDN , Power Delivery Network , PCB Signal integrity , IR drop , power , Allegro

System, PCB, & Package Design 

What's Good About Capture Locking Objects? The Secret's in the SPB16.3 Release!

The Allegro Design Entry CIS (Capture - Allegro flow) now includes an object locking…

• 1 min read
SPB16.3 , Design Entry CIS , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , SPB , design , OrCAD , Design Entry , Schematic , Allegro

System, PCB, & Package Design 

Cisco and Cadence Present Co-design Paper at DesignCon

Today at DesignCon, be sure to drop by Room 203 at 11:05 and see Cisco and Cadence…

• 1 min read
SiP , DesignCon , IC Package , Digital SiP design , Cisco , IC Packaging & SiP design , Physical layout and co-design

System, PCB, & Package Design 

Team Allegro Showing New PCB PDN Analysis Technology at DesignCon 2011

Today at DesignCon, drop by the Cadence booth to see TeamAllegro demonstrate the…

• 1 min read
PCB , PCB PI , PDN , PCB Signal and power integrity , Power Delivery Network , full wave , IR drop , power , Allegro

System, PCB, & Package Design 

Team Allegro to Boost Power of PCB PDN Solution – Sneak Peek at DesignCon 2011

The Cadence booth at DesignCon 2011 will provide visitors with a demonstration of…

• 1 min read
PCB , DesignCon , PCB PI , PDN , PCB Signal and power integrity , TeamAllegro , Power Delivery Network , full wave , IR drop , power , Allegro

Verification

What Could Be Simpler than a Request-Acknowledge Handshake?

My last few blog posts have included three corner-case conditions that led to bugs…

• 3 min read
Functional Verification , bugs , corner cases , formal , intent , assertions , simulation

Digital Design

Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End…

It hasn't been that long, but do you recall your new year's resolution? Eat healthier…

• 6 min read
ECO , conformal , Low Power , Encounter Test , gigahertz , giga-gate , 3D-IC , 3DIC , encounter digital implementation system , Mixed-Signal , encounter , rtl compiler , Silicon Realization , Digital Implementation , 3D , mixed signal , Digital end-to-end flow

Verification

The Role of Coverage in Formal Verification, Part 2 Continued…

Recall that three main questions need to be answered to attain coverage in formal…

• 3 min read
ABV , methodology , verification strategy , coverage , debug , Functional Verification , Formal Analysis , formal , Coverage-Driven Verification , CDV , Incisive , SVA , PSL , metric-driven verification , assertions , IEV , Incisive Enterprise Simulator (IES) , IFV

System, PCB, & Package Design 

What's Good About ADW’s Library Revision Manager and Browser? Check out the ADW16…

Here are just some of the new capabilities available in the ADW16.3 Allegro Design…

• less than a min read
PCB , SPB16.3 , Allegro Design Entry , DEHDL , Allegro 16.3 , SPB 16.3 , Allegro Design Workbench , Library flow , LRM , Design Entry HDL , component browser , design , Library Revision Manager , PCB design , Design Entry , ADW 16.3 , Librarians , ConceptHDL , library , Schematic , Allegro

Analog/Custom Design

SKILL for the Skilled: Continued Introduction to SKILL++

In my previous posting , which provided an introduction to SKILL++, I showed a simple…

• 6 min read
Team SKILL , hierarchy , walkCvHier , IC 6.1.5 , Virtuoso , flet , Lisp , Custom IC Design , SKILL++ , SKILL

Analog/Custom Design

Analog Assertion Based Verification Methodology – Reality or a Dream? (Part 1)

There is no doubt in my mind that assertions will play a significant role in analog…

• 4 min read
SystemVerilog , AMS , ABV , assertion-based , coverage , analog , Constraint-driven , Mixed-Signal , SVA , Verilog , assertion , ADE-GXL , PSL , assertions , random , MDV , Custom IC Design

Verification

SystemC: It's Neither Complicated Nor Belligerent!

I was recently talking to a customer who was looking to move up in abstraction from…

• 2 min read
High-Level Synthesis , TLM , C to Silicon , system , SystemC , C++ , ESL , System Design and Verification

Verification

Video: Distinguished Engineer Alok Jain on Formal and Assertion-Based Verification…

Kicking off 2011, my colleague Alok Jain -- a Distinguished Engineer at Cadence who…

• less than a min read
Alok Jain , IP , ABV , verification strategy , metric driven verification (MDV) , Functional Verification , Formal Analysis , ABVIP , formal , EDA360 , Coverage-Driven Verification , CDV , assertions , MDV , IEV , Incisive Enterprise Simulator (IES) , IFV , verification

Verification

The Role of Coverage in Formal Verification, Part 2

As noted in the prior installment of this series, there are three main questions…

• 4 min read
ABV , methodology , verification strategy , coverage , Functional Verification , Formal Analysis , Model-checking , formal , Coverage-Driven Verification , Incisive , SVA , PSL , assertions , IEV , IFV , verification

System, PCB, & Package Design 

What's Good About PCB SI Model Library Management? Look to SPB16.3 and See!

The SPB16.3 release of Design Entry HDL (DEHDL) provides an easier method for setting…

• 2 min read
PCB SI , PCB , SCM , SI , SPB16.3 , Allegro Design Entry , diff pairs , Signal Intregrity , DEHDL , Allegro 16.3 , SPB 16.3 , property , Library flow , SPB , PCB Editor , Constraint Manager , ASA , Allegro System Architect (ASA) , Front-end PCB design , design , PCB Signal integrity , PCB design , Design Entry , differential pairs , SI analysis and modeling , File Directives , Differential Pair Support , ConceptHDL , dml , model editor , Schematic

Verification

Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog

A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and…

• 3 min read
SystemVerilog , Specman , OVM ML , Testbench simulation , OVM e , EDA , e , e language , team specman , Aspect Oriented Programming , eRM , simulation , AOP , Functional Verificatioa , IES-XL
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