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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Verification

User Extensions to DUT Error

A question was raised to stackoverflow about how can one extend the dut _error()…

• 2 min read
Specman , e code , advanced verification , e language

Verification

App Note Spotlight - Introduction to Connect Modules

Welcome to the App Note Spotlight—a bi-weekly series where the XTeam highlights an…

• 3 min read
app note , Functional Verification , App Note Spotlight , Connect Module , mixed signal

Breakfast Bytes

Post-Silicon Compute

At the SEMI Strategic Materials Conference (SMC) a few weeks ago, Lucian Shifren…

• 6 min read
moore's law , ARM , power , DTCO

The India Circuit

Exciting Trends in 2018: An Interview with Jaswinder Ahuja

Jaswinder Ahuja is well-known to everyone in the semiconductor and electronics industry…

• 5 min read
mahindra & mahindra , Electronic System Design and Manufacturing , startups , Tata Motors , Maruti , electric vehicle , 2018 , ESDM

Whiteboard Wednesdays

Whiteboard Wednesdays - What to expect from TLM 2.0 Models for Memory Subsystems…

In this week's Whiteboard Wednesday, Vivek Nandakumar continues his explanation of…

• less than a min read
Whiteboard Wednesdays , Memory , TLM 2.0

Breakfast Bytes

Virtuoso System Design Platform Is Product of the Year

The title of this post says it all, but I'd better add a bit of color. Cadence was…

• 5 min read
virtuoso system design platform , Virtuoso , Allegro

Breakfast Bytes

2017: A Year in Breakfasts

So 2017 is over. Taylor Swift got into trouble for saying it was a great year and…

• 6 min read
security , Automotive , risc-v , nanosheet , broadcom , Qualcomm , 5nm , nanowire

Verification

Portable Stimulus User Gives Perspec PSS Technology Nearly Perfect Review

It’s always good to hear what real users think of products. Here is a very detailed…

• 3 min read

Verification

Register for the UVM Register Layer Webinar on January 12!

On Friday, January 12, Doulos is hosting a UVM Register Layer webinar, with the aim…

• less than a min read
webinar , Doulos , xcelium , uvm register layer

Breakfast Bytes

GLOBALFOUNDRIES 7nm

Earlier in the week, I wrote about my meeting with Gary Patton the day before GLOBALFOUNDRIES…

• 3 min read
GlobalFoundries , 7nm , EUV , IEDM

Analog/Custom Design

Automatically Reusing an SoC Testbench in AMS IP Verification

The complexity and size of mixed-signal designs in wireless, power management, automotive…

• 1 min read
AMS , mixed signal design , mixed-signal methodology , mixed signal solution , analog , Mixed-Signal , analog/mixed-signal , Virtuoso environment , mixed-signal verification

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (4 of 8)

Enabling Constraint-Driven Design With the pre-layout testbench built, populated…

• 5 min read
Serial link analysis , SI , Constraint Driven Design , Multi-Gigabit , PCIe , Signal Integrity , Sigrity

Breakfast Bytes

CES18 Preview

It's the start of a new year and that means it is the Consumer Electronics Show in…

• 9 min read
ces 2017 , deep learning , CES , audio , inception , atmos , Dolby , Tensilica , vision , neural networks

Breakfast Bytes

What is Meltdown? How Can It Affect Both Intel and Arm?

If you pay attention to anything to do with processors, security, or even investment…

• 8 min read
security , Intel , meltdown , x86 , ARM

Breakfast Bytes

What's For Breakfast? Video Preview January 8th to 12th 2018

https://youtu.be/txCnT3N4OSY Coming from Executive Briefing Center (camera Sean…

• less than a min read
Consumer Electronics Show , CES , CES2018 , semi , Virtuoso , ARM

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (3 of 8)

IBIS-AMI Modeling With initial PCB trace and via models in place for our hypothetical…

• 2 min read
Serial link analysis , SI , Multi-Gigabit , IBIS-AMI , PCIe , Signal Integrity , SerDes , Sigrity

Breakfast Bytes

Gary Patton on GF, IBM, 7nm, EUV, and More

At IEDM in December, I sat down with Gary Patton, CTO of GLOBALFOUNDRIES, to discuss…

• 8 min read
fab8 , 7lp , 12fdx , gf , gary patton , malta , 12lp , GlobalFoundries , 7nm

The India Circuit

Face Recognition and Hackathon: An Unlikely and Innovative Combination

Happy New Year! While most other folks are just easing back to work, those of us…

• 4 min read
VLSI & Embedded Systems Design Conference , Tensilica , Tensilica Xtensa , neural networks , CNN , face recognition

Breakfast Bytes

Intel 10nm

At IEDM last month, Intel announced details of their 10nm process. Later the same…

• 5 min read
Intel , coag , FinFET , 10nm , Breakfast Bytes
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