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Featured

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
Corporate 25 Jun 2026 • 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
Corporate 24 Jun 2026 • 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
Corporate 23 Jun 2026 • 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
Corporate 22 Jun 2026 • 8 min read
featured , physical ai , HGR , AI , Honda
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Blog - Post List
Latest blogs

RF /マイクロ波設計

μWaveRiders:Cadence AWR Design Environment V15.03 ソフトウェアのリリースをハイライト

Team RF "μWaveRiders" ブログシリーズがCadence AWR RF製品のためのショーケースとしてデビューします。月ごとの話題はCadence…

RF Design Japan 14 Jan 2021 • less than a min read
RF , RF Simulation , AWR Analyst , Circuit simulation , AWR Design Environment , awr , Analog Simulation , AWR Design Environment V15.03 , AWR AXIEM , RF design , AXIEM 3D Planar Simulator , japanese blog , AWR Design Environment release

RF Engineering

μWaveRiders: Cadence AWR Design Environment V15.03 Software Release Highlights

The Cadence AWR Design Environment V15.03 production release with many enhancements…

TeamAWR 13 Jan 2021 • 2 min read
RF , RF Simulation , AWR Analyst , Circuit simulation , AWR Design Environment , Analog Simulation , AWR Design Environment V15.03 , AWR AXIEM , RF design , AXIEM 3D Planar Simulator , AWR Design Environment release

カスタムIC/ミックスシグナル

Virtuosity: DSPF Virtuoso EMIR解析フローのデビュー

読者のみなさん、こんにちは! 設計エンジニアの生産性を継続的に改善することは、ケイデンスが従う戦略の中心であり、プロダクト全体でさまざまな革新と改善された機能をもたらしました…

Custom IC Japan 13 Jan 2021 • less than a min read
Voltus-Fi , EMIR Analysis , ADE Explorer , Voltus-Fi-XL , MMSIM , DSPF , EMIR Extraction , Spectre , Quantus Extraction Solution , Virtuosity , ICADVM20.1 , analog design , japanese blog , signoff , Custom IC Design , Virtuoso Layout Suite , simulation , IC6.1.8 , ADE Assembler

System, PCB, & Package Design 

BoardSurfers: How to Add Fanouts Using Standard Via Structures

An increase in design complexity has forced designers to take novel approaches to…

avijeet 13 Jan 2021 • 5 min read
17.4-QIR2 , 17.4-2019 , Allegro PCB Editor

Breakfast Bytes

Cadence/Arm Event on Optimizing High-End Arm Processors in Advanced Nodes

On January 21 from 8:00am to 11:00am (PST), Cadence and Arm are presenting a joint…

Paul McLellan 13 Jan 2021 • 3 min read
Genus , cortex-a78 , neoverse , Innovus , digital full flow , cortex-x1 , ARM

PCB設計/ICパッケージ設計

2021年1月リリース、Cadence OrCAD / Allegro17.4-2019 HotFix SPB17.40.013の新機能ハイライト

OrCAD® および Allegro® の 17.4 HotFix 013 (QIR 2、アプリケーションのスプラッシュ画面で は ”2021” と示されています…

SPB Japan 13 Jan 2021 • less than a min read
PCB , 17.4 , OrCAD Capture , PSpiceA/D , PSPICE , PCB Editor , 17.4-2019 , Allegro System Capture , japanese blog , Pulse

カスタムIC/ミックスシグナル

Virtuoso Meets Maxwell: 精度を満足させるための階層的な電磁界モデリング

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

Custom IC Japan 12 Jan 2021 • less than a min read
Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Electromagnetic analysis , EMX , Quantus Extraction Solution , RF design , ICADVM20.1 , japanese blog , Custom IC Design , VMM

System, PCB, & Package Design 

IC Packagers: Exciting New Updates and Reasons to Move to 17.4 Hotfix 013

Welcome to a brand-new year, everyone! As we welcome in 2021, we also welcome the…

Tyler 12 Jan 2021 • 4 min read
IC Packaging and SiP Design , 17.4 , Allegro Package Designer , 17.4-2019

Breakfast Bytes

IEDM Opening Keynote

At IEDM in December, the opening keynote (technically "Plenary 1") was by Sri Samevadam…

Paul McLellan 12 Jan 2021 • 4 min read

カスタムIC/ミックスシグナル

Start Your Engines: Electrical信号からReal Numberへの変換のためのミックスシグナル・モデリングの方法

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

Custom IC Japan 11 Jan 2021 • less than a min read
real number modeling , electrical to real conversion , AMS-Designer , Start Your Engines , analog/mixed-signal , mixed signal , japanese blog , mixed-signal verification

Breakfast Bytes

Young People Program at DATE 2021

Are you a young person? Are you doing a PhD? Then you should know that Cadence is…

Paul McLellan 11 Jan 2021 • 6 min read
DATE , Cadence Academic Network , young persons programme , date 2021 , ypp

Breakfast Bytes

Sunday Brunch Video for 10th January 2021

https://youtu.be/gt4GiLtoJ4M Made at Castle Rock Park (camera Ziyue Zhang) Monday…

Paul McLellan 10 Jan 2021 • less than a min read
sunday brunch

System, PCB, & Package Design 

Cadence OrCAD and Allegro 17.4-2019 HotFix SPB17.40.013 is Now Available

The HotFix 013 (QIR 2, indicated as 2021 in the application splash screens) update…

AllegroReleaseTeam 8 Jan 2021 • 3 min read
17.4 , OrCAD Capture , EDM , ECAD-MCAD Library Creator , PCB design , Allegro System Capture , Allegro PCB Editor , Pulse

Breakfast Bytes

Breakfast Nibbles 2021: Predictions for the Year, part 3

The first part of my predictions for 2021 was two days ago, and the second part was…

Paul McLellan 8 Jan 2021 • 7 min read
predictions , chiplet , 3nm , more than Moore , 5nm

PCB設計/ICパッケージ設計

(P)SpiceItUp: PSpice A/Dを用いた設計の検証と最適化

PSpice® A/Dは、OrCAD®およびAllegro®ツールと統合が可能なフル機能のアナログ/ミックスシグナル用シミュレーターです。PSpice A/Dを用いることで…

SPB Japan 7 Jan 2021 • less than a min read
17.4 , PSpiceA/D , Capture CIS , PSPICE , 17.4-2019 , japanese blog

Verification

Higher FLASH Throughput for Your Next SoC Design

Memory is an important part of every electronic system, still it is increasingly…

Chetans 7 Jan 2021 • 1 min read
Verification IP , Memory , flash , VIP , JEDEC , storage

Breakfast Bytes

Breakfast Nibbles 2021: Predictions for the Year, part 2

The first half of my predictions for 2021 was yesterday. You should probably start…

Paul McLellan 7 Jan 2021 • 4 min read
2021 , predictions

Breakfast Bytes

Breakfast Nibbles 2021: Predictions for the Year, part 1

It's 2021 finally. Although 2020 was actually a good year for the semiconductor industry…

Paul McLellan 6 Jan 2021 • 5 min read
5G , predictions , deep learning , hyperscalar datacenters , mobile , AI

Breakfast Bytes

The Biggest Security Breach Ever

Over the Christmas break, the biggest security breach ever came to light. It is assumed…

Paul McLellan 5 Jan 2021 • 4 min read
security , solarwinds , backdoor
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