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Featured

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

Corporate
Corporate 13 Jul 2026 • 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant

Artificial Intelligence (AI)

You'll Still Do the Work—You Just Won't Do the Boring Part

Agentic AI is about to change your flow. Here's what actually shifts—and why the…

Corporate
Corporate 13 Jul 2026 • 5 min read
artificial intelligence , featured , agentic ai , NVIDIA , AI for design

Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
Corporate 30 Jun 2026 • 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
Corporate 25 Jun 2026 • 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai
cdns - all_blogs_categories

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Blog - Post List
Latest blogs

Digital Design

Encounter Screencast: Editing Wires More Quickly With Bindkeys

The Encounter Digital Implementation System offers interactive wire editing capabilities…

BobD 21 Jan 2010 • 1 min read
Wire Editor , encounter digital implementation system , Digital Implementation , bindkeys

System, PCB, & Package Design 

What's Good About SigXp UI Changes? SPB16.3 Has Many New Enhancements!

The SPB16.3 SigXP UI has been enhanced to focus on giving users better access to…

Jerry GenPart 20 Jan 2010 • 8 min read
SigXP UI , layer stacks , SPB 16.3 , PCB design , Allegro

Digital Design

Sometimes It's The Little Things: Working With Square Brackets in Encounter

Good news! A long-standing source of irritation for Encounter users has been addressed…

BobD 15 Jan 2010 • 1 min read
Ease of Use , Encounter Digital Implementation System 8.1

Verification

Android System Verification Part 6

Welcome to Part 6 of Android System Verification. It's getting hard to trace back…

jasona 15 Jan 2010 • 3 min read
emulator , android , System Design and Verification , system

RF Engineering

Using The Composite Triple Beat Source to Speed up QPSS Analysis

Say you have a design with 4 input frequencies: 3164M (vco), 1449M (tone0), 1456M…

Tawna 14 Jan 2010 • 2 min read
RFIC , QPSS Analysis , CTB , Virtuoso Spectre , Spectre RF , MMSIM , RF Block Simulation , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , spectreRF , RF design , harmonic balance , Composite Triple Beat

SoC and IP

The Flash Factor for Consumer Devices: Will NAND Flash and Hard Disk Storage Coexist…

By Steve Leibson for Denali Software If you spend a lot of time reading and…

Denali Blog 13 Jan 2010 • 4 min read

Verification

Changing The "F" in RTFM to "Fantastic"

Talk about unsung -- tech writers just don't get the credit they deserve. They sit…

Team genIES 12 Jan 2010 • 1 min read
Tech Pubs , Functional Verification , Incisive , Kit , IES , IES-XL

Analog/Custom Design

Virtuoso Layout Migrate - 614 Enhancements

Hi, I'm Thibault Alix and I have been working with the VLM team for two years. I…

archive 11 Jan 2010 • 1 min read
Layout Migrate , Virtuoso , IC 6.1.4 , VLM , Custim IC Design , SKILL

Verification

AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

The Open Verification Component (OVC) defined by the official OVM User Guide in the…

Team genIES 8 Jan 2010 • less than a min read
SystemVerilog , uvm , OVM ML , Functional Verification , OVM , OVM SV , Signal Integrity , AMIQ , IES , IES-XL

System, PCB, & Package Design 

What's Good About Allegro Placement Replication / Fine Tuning? - Look to SPB16.3…

Placement replication was introduced in Allegro PCB Editor SPB16.2. At that time…

Jerry GenPart 6 Jan 2010 • 5 min read
SPB 16.2 , Placement Replication , SPB 16.3 , Allegroro , PCB design

SoC and IP

Low Power DDR Options -- From the Trenches

by Marc Greenberg, Director of Technical Marketing, Denali Software Momentum…

Denali Blog 6 Jan 2010 • 3 min read

Verification

Back to Work in 2010

It's back to work in 2010. Thanks for all the great feedback in 2009. I plan to continue…

jasona 6 Jan 2010 • 2 min read
global warming , System Design and Verification , code offets , linux

Digital Design

Design Signoff Begins In Implementation

As an ex-design engineer now working in EDA, I am often privileged to see advanced…

PeteMc 6 Jan 2010 • 1 min read
dynamic rail analysis , Static timing analysis , SI , Early Rail Analysis , ets , cadence , EDI system , Signoff Analysis , encounter digital implementation system , EPS , Signal Integrity , Cadence Encounter Power System , Digital Implementation , crosstalk , CeltIC , tapeout , design closure , encounter power system , Encounter Timing System , timing convergence , "SoC-Encounter" , blog

Digital Design

Trying to Figure Out Social Media? Ron Ploof Says "Read This First"

Left to Right: Ron Ploof, Bob Dwyer Photo Credit: brillianthue "As a New Media evangelist…

BobD 5 Jan 2010 • 6 min read
Facebook Twitter , New Media , EDA , Social Media , Ron Ploof

Verification

Is The Industry Ready For Mainstream Adoption of Higher Abstraction?

I was recently part of an industry wide interview conducted by Clive "Max" Maxfield…

Steve Brown 4 Jan 2010 • 1 min read
TLM , System Design and Verification , SystemC

RF Engineering

NPORT S-Parameter Model Enhancements

In MMSIM 7.2, two new parameters have been added to the Spectre nport primitive:…

Tawna 30 Dec 2009 • 1 min read
Circuit simulation , MMSIM71 , RFIC , Virtuoso Spectre , Spectre RF , MMSIM , RF Block Simulation , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , spectreRF , Spectre , RF design , Circuit Design , harmonic balance

Verification

Adam’s Verification Top 10 In '10

I love top 10 lists. Not so much for the drama of the count-down, but for arguments…

Adam Sherer 29 Dec 2009 • 3 min read
performance , SystemVerilog , Real Value Modeling , OVM ML , Functional Verification , CPF , OVM , OVM e , Incisive , OVM SV , e , Mixed-Signal , Simulation acceleration , SystemC , VHDL , IES , OVM SC

Verification

Android System Verification Part 5

In the previous article I introduced the use of Specman for generating sequences…

jasona 29 Dec 2009 • 2 min read
GPS , android , System Design and Verification

System, PCB, & Package Design 

What's Good About Reflection?

What's good about it is that we don't need to reflect occasionally. We can reflect…

Jerry GenPart 28 Dec 2009 • 1 min read
PCB design , reflection , Allegro
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