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Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

Corporate
• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant

Artificial Intelligence (AI)

You'll Still Do the Work—You Just Won't Do the Boring Part

Agentic AI is about to change your flow. Here's what actually shifts—and why the…

Corporate
• 5 min read
artificial intelligence , featured , agentic ai , NVIDIA , AI for design

Artificial Intelligence (AI)

The Feedback Loop Is the Moat

Every verification and design team I talk to is building agents right now. The demos…

HS202601273724
• 14 min read
featured , AI in chip design , GenAI , AI/ML
cdns - all_blogs_categories

Blog - Post List
Latest blogs

RF Engineering

Join us at the Cadence booth at the International Microwave Symposium

If you listened to Tom's advice on this blog two months ago and registered for the…

• 1 min read
RFIC , Spectre RF , Virtuoso , RF design , International Microwave Symposium

Verification

New IntelliGen Statistics Collection Utilility

As noted in white papers , prior posts , and the Specman documentation, since IntelliGen…

• less than a min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , Incisive , e , team specman , Incisive Enterprise Simulator (IES) , IES , IES-XL

Verification

Synthesis Really DOES Need to Change

A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, …

• 2 min read
System Design and Verification , rtl compiler , C-to-Silicon Compiler

Analog/Custom Design

Things You Didn't Know About Virtuoso: Editing Properties

When I was growing up, my mother would usually bake a ham for Christmas dinner. She…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Digital Design

MarCom 2009 - New, Exciting, Educational

As a Marketing Communications professional, I am always looking for creative ways…

• 2 min read
EDI , EDI system , encounter digital implementation system , Digital Implementation

SoC and IP

The Great Escape, Part II: How These Companies Exited the DRAM Business

Case Histories of Significant DRAM Market Withdrawals : This article continues…

• 18 min read

Verification

Inside Cadence: "Stars & Strikes" charity event

Allow me to make a brief digression from EDA technology blogging to give you all…

• 1 min read
Functional Verification , charity benefit , Stars and Strikes festival

Verification

Where's the Bridge to Cross the Great Divide?

At this year's Embedded System Conference in San Jose there was a panel with the…

• 8 min read
windows , dwarfdump , VMware , Embedded Systems Conference 2009 , ISX , Hardware/software co-verification , linux

Verification

New "E" text editor and e templates

Imagine Team Specman's surprise when we came across this article on Slashdot about…

• 1 min read
IEEE 1647 , eclipse , Specman , Functional Verification , e , AMIQ , verification , IES-XL

SoC and IP

Denali MemCon leads "Memory Week" in Silicon Valley, June 22-25

Denali MemCon 2009, scheduled for the Santa Clara Hyatt Regency on June 22-24, is…

• 1 min read

Analog/Custom Design

Things You Didn't Know About Virtuoso: Navigator Assistant

Have you ever found yourself working with a massive schematic having to constantly…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

SoC and IP

The Great Escape, Part I: How These Companies Exited the DRAM Business

Updated version to reflect correction to company naming due to errors in original…

• 8 min read

Verification

Report from CDNLive! EMEA 2009

CDNLive! in Munich had it all - stimulating customer papers, demonstrations of new…

• 1 min read
ABV , CDNLive , Functional Verification , OVM , VIP , TLA , MDV

Verification

Tech Tip: Weighting Generation of "Extreme" Values

[ Team Specman welcomes guest blogger Vitaly Lagoon, an Architect in the Generation…

• 1 min read
IntelliGen , Specman , Verification methodology , Functional Verification , Incisive , e , team specman , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Verification

Heads-up: DVClub Boston Coming Up On June 1

Back on March 19 here in Silicon Valley, verification guru Brian Bailey gave a great…

• less than a min read
events , verification strategy , Functional Verification , DVClub

SoC and IP

Memory Company Financials, 1Q09

1Q09 Better than 4Q08, but still terrible: Memory makers continued to suffer…

• 8 min read

Analog/Custom Design

Things You Didn't Know About Virtuoso: Tabs and Bookmarks

Do you remember the first time you used a browser with tabs? All of a sudden, there…

• 2 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

Way Worse Than The Real Thing

This week Cadence and Virtutech announced a collaborative effort to bring together…

• 2 min read
cdnlive! emea 2009 , System Design and Verification , Incisive Enterprise Simulator , embedded software , Incisive , Coverage Driven Verification for Embedded Software , embedded SW engineer , ISX , Hardware/software co-verification , ESL , architect , Virtutech , Coverage Driven Verification

System, PCB, & Package Design 

Innovative Approach to Optimized FPGA Pin Assignment

Cadence has been a leader in silicon-package and package-board co-design for over…

• less than a min read
FPGA-PCB Co-Design , PCB design , FPGA
CDNS - Fix Layout Hompage