Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

Corporate
• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant

Artificial Intelligence (AI)

You'll Still Do the Work—You Just Won't Do the Boring Part

Agentic AI is about to change your flow. Here's what actually shifts—and why the…

Corporate
• 5 min read
artificial intelligence , featured , agentic ai , NVIDIA , AI for design

Artificial Intelligence (AI)

The Feedback Loop Is the Moat

Every verification and design team I talk to is building agents right now. The demos…

Hamid Shojaei
• 14 min read
featured , AI in chip design , GenAI , AI/ML
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About Dynamic Fillets in Allegro PCB Editor? Check out the SPB16.2 Release

The existing Fillet application, a function of the Gloss routine, has been enhanced…

• 1 min read
SPB 16.2 , PCB Editor , Allegroro , PCB design , Dynamic Fillets , t-juntions

System, PCB, & Package Design 

It’s All In The Metrics

You could be forgiven for thinking that this was going to be a discussion of the…

• 3 min read
Allegro Design Workbench , PCB design , metrics , enterprise integration

Digital Design

Does Noise Analysis Accuracy Really Matter?

There have been a lot of new faces springing up in the signoff analysis market over…

• 2 min read
Static timing analysis , Signoff Analysis , STA , Advanced Node , Mixed-Signal , 8.1 , Encounter Digital Implementation , CeltIC NDC , Global Timing Debug , SSTA , "SoC-Encounter"

SoC and IP

Taiwan Memory Company (TMC), Part III

"EDIT: I have corrected Etron's 2007 P& L entry to show a net profit of 39M instead…

• 7 min read

Verification

New eDocs Makes Documenting Fun!

Documentation. This single word tends to sends shivers up the spine of many an engineer…

• 3 min read
Specman , Functional Verification , e , specman elite , OOP , hvl , AOP , verification

Verification

Tech Tip: Determining When a Sequence Has Finished

Imagine the complex scenario whereby you start the *same* sequence on multiple sub…

• 1 min read
IEEE 1647 , Specman , Functional Verification , OVM e , e , Aspect Oriented Programming , eRM , AOP

Verification

Users Report on OVM in a Multi-Language World: Results From DVCon

The OVM user reports from Xilinx, SiRF, and ST at the DVCon luncheon were real engineer…

• 1 min read
SystemVerilog , OVM , OVM e , OVM SV , e , DVcon , SystemC , OVM SC

Verification

DVCon '09 SaaS Panel Thoughts, Part 1

[Preface / Disclaimer: I haven't yet had the pleasure of working closely with Cadence…

• 1 min read
SaaS , metric driven verification (MDV) , Functional Verification , Coverage-Driven Verification , CDV , Harry The ASIC Guy , DVcon , coverage driven verification (CDV)

System, PCB, & Package Design 

Everything You Want to Know About APD / SiP 16.2 - Bill Acito Webinar on March 1…

(N ote: Click here to view Bill Acito's webinar.) If you caught Jerry GenPart 's…

• less than a min read
SiP , 16.2 , APD , IC Packaging & SiP design , webinar , HDI

System, PCB, & Package Design 

What's Good About Allegro® Design Entry HDL – User Customizations? You Tell Me!

Well ... if you like tweaking and tuning an environment to suit your needs, Allegro…

• 1 min read
SPB 16.2 , CDNLive! 2008 , DEHDL , PCB design , SPB16.01 , Allegro

Digital Design

How To Use I/O Rows - It's a Snap!

Have you ever tried manually moving IO cells in your design and thought: "This would…

• 1 min read
encounter 8.1 , Floorplanning , Digital Implementation , i/o rows

Verification

SystemC Save and Restore Part 2 - Advanced Usage

In my last post I discussed how to use save / restore in the Cadence Incisive Simulator…

• 3 min read
System Design and Verification , embedded software , Incisive , virual platform , virtual prototype , George Frazier , SystemC , Hardware/software co-verification , ESL

Digital Design

Talk "Low Power" With The Experts

I am very excited about an event that Cadence low-power R&D and technical experts…

• less than a min read
Low Power , Digital Implementation forums , Low-Power , Power-Efficient Design , encounter , Logic Design , 8.1 , Digital Implementation , Encounter Digital Implementation , Encounter Digital Implementation System 8.1 , verification

Analog/Custom Design

Virtuoso MMSIM, Bringing Accuracy and Performance to a Neighborhood Near You

In order to bring our technology and developers closer to you the MMSIM team is…

• less than a min read
MMSIM , workshop , seminar , Custom IC Design

Digital Design

Constraint Construction: What's Its Function? Part 3 of 4

Part 3. EXCEPTION PATHS: For Every Rule, There Is An Exception More often than not…

• 2 min read
Constraint Design , STA , Encounter Digital Implementation , Encounter Timing System

Verification

OVM-e Sequence API Brings Increased Flexibility

Specman 8.2s2 adds new Application Programming Interface (API) methods to sequence…

• 6 min read
Specman , Functional Verification , API , OVM , e , eRM

Verification

Quick Tip: Searching for Special Characters in Cadence Help

[Team Specman welcomes back the Technical Publications Team to guest blog] A logical…

• less than a min read
Tech Pubs , Functional Verification , Cadence Help

Analog/Custom Design

The Value of Virtuoso as an Ecosystem

An ecosystem as defined by Webster's is a "system formed by the interaction of a…

• 3 min read
Virtuoso , Custom IC Design , C++ , SKILL

System, PCB, & Package Design 

What's Good About Coplanar Waveguide Support in PCB SI? It's now in SPB16.2!

Coplaner waveguides (CPW) are widely used in packaging, high speed designs and on…

• 5 min read
SPB 16.2 , CPW Extraction , PCB design , coplanar
CDNS - Fix Layout Hompage