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Featured

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
Corporate 2 Oct 2025 • 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
Corporate 1 Oct 2025 • 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
Vinod Khera 28 Sep 2025 • 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 25 Sep 2025 • 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
cdns - all_blogs_categories

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Blog - Post List

Latest blogs

Breakfast Bytes

Automotive at CES

Automotive was huge at CES. A lot of it went for the glamour without really having…

Paul McLellan 19 Jan 2017 • 3 min read
Automotive , NVIDIA , Qualcomm

Whiteboard Wednesdays

Whiteboard Wednesdays - Interconnect Design Verification Challenges

In this week's Whiteboard Wednesdays video, Nimrod Reiss takes a closer look at the…

References4U 17 Jan 2017 • less than a min read
Verification IP , Whiteboard Wednesdays , VIP , MIPI , MIPI protocols , Nimrod Reiss , verification

Breakfast Bytes

Security in 2016 and 2017

It's the start of the year, plus the Consumer Electronics Show is over. I've already…

Paul McLellan 17 Jan 2017 • 3 min read
security , botnets , mirai , drones , Singapore

Analog/Custom Design

Virtuoso Video Diary: Using the Hierarchical Color Locking Check

As you incrementally build your design and decompose the layout geometry into masks…

mita 16 Jan 2017 • 2 min read
dbLock , Hierarchical Color Locking Conflicts , Multiple Patterning Technology , HCL , Coloring Engine , Virtuoso Video Diary , Hierarchical Color Locking Check , multi-patterning technology , Custom IC Design , MPT

Academic Network

Cadence Academic Network Events in Russia

Despite all of the recent political tensions, Russia remains an attractive market…

Anton Klotz 16 Jan 2017 • 2 min read
MIET , Cadence Academic Network , MEPHI , RusNano , Russia

Breakfast Bytes

5G is Coming. Qualcomm Keynote at CES

Steve Mollenkopf, the CEO of Qualcomm, gave one of the keynotes at the Consumer Electronics…

Paul McLellan 16 Jan 2017 • 4 min read
5G , Automotive , Consumer Electronics Show , CES , IoT , Qualcomm , mobile

Breakfast Bytes

Bluetooth 5, 4.2, Bluetooth Classic, and Bluetooth LE...Confused Yet?

What is Bluetooth 5? 4.2? Bluetooth Classic? Bluetooth Smart? Low Energy? The naming…

Paul McLellan 13 Jan 2017 • 6 min read
BLE , bluetooth , bluetooth 4.2 , Bluetooth 5.0 , Breakfast Bytes

Breakfast Bytes

Security the Google Way

The latest RISC-V workshop was held at Google. In the middle of the day, there was…

Paul McLellan 12 Jan 2017 • 3 min read
security , risc-v , nsa , google , bios lockdown , rowhammer , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview January 16th to 20th 2017

https://youtu.be/ympju1edOh8 Coming from my office at Cadence Monday: Review…

Paul McLellan 11 Jan 2017 • less than a min read
security , Automotive , Consumer Electronics Show , CES , Qualcomm , ADAS , privacy , esd alliance

Breakfast Bytes

RISCy Business: Next Hogan Evening at ESD Alliance Is RISC-V

The ESD Alliance Emerging Companies have been organizing a series of evening events…

Paul McLellan 11 Jan 2017 • 2 min read
risc-v , Cadence Academic Network , ESDA , risc-v foundation , Hogan , Jim Hogan , esd allliance , Breakfast Bytes , sifive

Breakfast Bytes

CES Highlights

Happy New Year, and the first week of January means it is the Consumer Electronics…

Paul McLellan 10 Jan 2017 • 4 min read
Consumer Electronics Show , CES , autonomous , virtual reality , drone , ADAS , augmented reality , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of Ethernet: The World Before Ethernet

In this week's Whiteboard Wednesdays video, the first in a three-part series on Ethernet…

References4U 10 Jan 2017 • less than a min read
Verification IP , VIP , Ethernet

Breakfast Bytes

ACE Awards: Palladium Z1 Team Is Design Team of the Year

Every year, UBM, the parent company of EE TImes and EDN (and the organizer of several…

Paul McLellan 9 Jan 2017 • 6 min read
design team of the year , palladium z1 , Palladium , ace awards , Emulation , Breakfast Bytes , ubm

Breakfast Bytes

What's For Breakfast? Video Preview January 9th to 13th 2017

https://youtu.be/33fiVk2BoKo Coming from Flamingo Hotel, Las Vegas at during…

Paul McLellan 7 Jan 2017 • less than a min read
security , risc-v , ACE award , Consumer Electronics Show , CES , Palladium , encryption , privacy , esd alliance

Breakfast Bytes

MediaTek's Experience with Perspec

At CDNLive in Taiwan last year, MediaTek presented their experiences with Perspec…

Paul McLellan 6 Jan 2017 • 3 min read
CDNLive , Perspec , cdnlive taiwan , mediatek , System Verifier , Breakfast Bytes

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Vince’s Favorite Usability Features! (Reason 10…

Most of the PCB designers I know are creatures of habit just like I was... we…

vdilello 5 Jan 2017 • 7 min read
Allegro 17.2 , PCB design , Allegro PCB Editor , Why Move Up to 17.2

Breakfast Bytes

IEDM: Coventor Panel on BEOL Challenges

At the recent IEDM in San Francisco, Coventor organized a panel titled BEOL Barricades…

Paul McLellan 5 Jan 2017 • 6 min read
tokyo electron , cobalt , copper , Samsung , Lam Research , Coventor , GlobalFoundries , beol , umc , rubidium , Breakfast Bytes , liner

Verification

Bugs, Problems, Issues, and Features

There’s no better way to demonstrate the value of a verification tool than to find…

tomacadence 4 Jan 2017 • 3 min read
performance , uvm , pswg , Functional Verification , Perspec , OVM , issue , bug , feature , Accellera , Problem , portable stimulus

Breakfast Bytes

Dolby Atmos and Tensilica

Dolby Laboratories was founded by Ray Dolby. I always thought he was English, but…

Paul McLellan 4 Jan 2017 • 3 min read
Consumer Electronics Show , CES , audio dsp , atmos , HiFi , Dolby , Tensilica , television , Breakfast Bytes
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