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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

SoC and IP

Why Software-Based GPS Is Great for Location-Based IoT Applications

At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo…

• 1 min read

Breakfast Bytes

How Many Journalists per Square Acre?

It doesn't matter how low your standard is for science journalism, the journalists…

• 5 min read
kilowatt , degree , kilowatt hour

Analog/Custom Design

Take Advantage of Advancements in Real Number Modeling and Simulation

Verification is the top challenge in mixed-signal design. Bringing analog and digital…

• 2 min read
real number modeling , analog , Mixed-Signal , RNM , mixed-signal verification

Verification

Xcelium and Cavium: What’s the Deal?

So—you may have heard that Xcelium Parallel Simulator is available on Arm servers…

• 1 min read
thunder x2 , video , Cavium , xcelium

Breakfast Bytes

Patents: Licensed by the Ton

I wrote recently about What Happens in a Patent Lawsuit? Today, I want to look at…

• 8 min read
patent , troll , non-practising entity , cross-licensing , npe

SoC and IP

Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would…

• 4 min read
Galileo , GPS , IoT , Tensilica DSPs

Breakfast Bytes

How Do You Get to Be CEO?

I wrote last week about Being CEO and I said that I'd done it twice in my career…

• 6 min read
board , management , chief executive officer , leadership , CEO

Analog/Custom Design

Virtuosity: New Eye Diagram Measurements

The Eye Diagram assistant in Virtuoso Visualization and Analysis allows you to create…

• 2 min read
Eye Mask , Analog Design Environment , ViVa-XL , ADE Explorer , Explorer , ADE XL , ADE , eye diagram , Analog Design Environment , ViVA , ADE-XL , Virtuosity , Custom IC Design , ADE Assembler

Verification

New AMBA 5 ACE/AXI Specification: More About Atomic Transactions

As discussed in the previous installment of this blog, a new class of atomic transactions…

• 1 min read
amba5 , ACE5 , AXI5 , Atomic Transactions

Breakfast Bytes

What's For Breakfast? Video Preview February 26th to March 2nd 2018

https://youtu.be/wq86edcqTdw Coming from Building 10 lobby (camera Sean) Monday…

• less than a min read
fec , patent , journalism , Embedded World , forward error correction

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)

Backchannel Training Another capability related to equalization adaptation is backchannel…

• 2 min read
Serial link analysis , IBIS-AMI , PCIe , Signal Integrity , Backchannel , Sigrity

Breakfast Bytes

Paul Kocher: Differential Power Analysis and Spectre

Paul Kocher is a legend in security. A couple of weeks ago SiFive hosted a seminar…

• 11 min read
security , risc-v , Spectre , Paul Kocher , sifive

Digital Design

Wind of Change in Hardware Design

After months of freezing temperatures in Pittsburgh, a 78 degree wind hit me as I…

• 2 min read
High-Level Synthesis , deep learning , machine learning , Stratus , HLS

Breakfast Bytes

Is Big Brother Watching You?

I recently came across a fascinating piece by Paramal Satyal . He is Nepalese although…

• 6 min read
security , cookie , webbkoll , advertising

Verification

Coming to DVCon? It's Not Too Late to Sign Up!

Are you coming to DVCon this year? It’s right around the corner, but it’s not too…

• 1 min read
Functional Verification , DVcon 2018 , tutorials , event

Whiteboard Wednesdays

Whiteboard Wednesdays - Using DDR PHY Power Features to Reduce Power Dissipation

In this week's Whiteboard Wednesday video, Marc Greenberg explains the ways to optimize…

• less than a min read
Whiteboard Wednesdays , DDR PHY , Low Power DDR

Breakfast Bytes

embedded world 2018 Preview

It's nearly time for embedded world 2018 (yes, it likes to be trendy and put it all…

• 5 min read
Automotive , embedded world 2018 , 22fdx , Vision DSP , Tensilica , ADAS , GlobalFoundries

Breakfast Bytes

Why 1 Is Not a Prime Number

It's Presidents' Day and Cadence is on holiday. So time for me to write about something…

• 6 min read
PI , fundamental theorem of algebra , fundamental theorem of arithmetic , tau , central dogma of biology

Breakfast Bytes

Suddenly You Are CEO. What Do You Do Next?

We've covered sales , marketing , and application engineering . Let's go up to the…

• 7 min read
board , chief executive officer , CEO
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