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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

The Future of EDA: The View from Academia

There was a recent panel discussion at Cadence on the future of EDA. Of course the…

• 6 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Verification

A Personal History of Functional Verification

In my most recent blog post , I summarized some of the key points from an October…

• 4 min read
ASIC , uvm , pswg , formal. Verisity , Functional Verification , System Design and Verification , OVM , System Development Suite , constrained-random , Simulation acceleration , Accellera , metric-driven verification , Virtual Platforms , Hardware/software co-verification , simulation , FPGA , System Design and Verification

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Via Structures - The Next Generation High Speed…

Via transitions are very common for signals. And in high speed frequencies, these…

• 2 min read
diff pairs , Signal Intregrity , High Speed , PCB design , differential pairs , SI analysis and modeling , Differential Pair Support , Why Move Up to 17.2

Breakfast Bytes

RISC-V 5th Workshop Preview

The 5th RISC-V workshop is coming up on November 29 and 30 on the Google Quad campus…

• 3 min read
risc-v , risc-v foundation , google , risc-v workshop , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview November 21st to 25th

https://youtu.be/dHvlzjjH9SA Monday: The Academic Panel: the Academics Go First…

• less than a min read
Alberto , thanksgiving , Cadence Academic Network , academia , Stanford , cal , industry , UC Berkeley

Breakfast Bytes

JasperGold: Thoroughbred Performance

At the largest gathering of formal verification (FV) engineers in the world, also…

• 6 min read
JUG , formal , Visualize , Jasper , jaspergold apps , JasperGold , Breakfast Bytes , verification

System, PCB, & Package Design 

Why SerDes Signaling Is Trending Towards PAM Encoded Signals

What’s the difference between NRZ, PAM-3 and PAM-4? Here are three graphs that clearly…

• 2 min read
Serial link analysis , PAM-4 , Sigrity , PAM-3

Breakfast Bytes

Jürgen Went From Mobile to Automotive—What Did He Find?

After ARM on the first day, the keynote on the second day of DVCon was by NXP. For…

• 8 min read
Automotive , NXP , DVcon , ARM , Breakfast Bytes , verification

Whiteboard Wednesdays

Whiteboard Wednesdays - MIPI Alliance Interfaces

In this week's Whiteboard Wednesdays video, Moshik Rubin takes a closer look at the…

• less than a min read
Whiteboard Wednesdays , MIPI , MIPI protocols , DSI , CSI2

Breakfast Bytes

What Is the ARM ARM?

The first ARM is the ARM we all know, Advanced RISC Machines (the A originally stood…

• 5 min read
Jasper User Group , JUG , Jasper , ARM , JasperGold , arm arm , Breakfast Bytes , Formal verification

Breakfast Bytes

Red Hat's Mr. ARM Talks Open Source

Jon Masters is in an odd position—he is the chief ARM architect at Red Hat. Since…

• 8 min read
open source hardware , arm servers , red hat , open source software , open source , jon masters , linux , Breakfast Bytes

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Tabbed Routing - The Next Generation High Speed…

Improve Route Channel Utilization with Tabbed Routing Tabbed routing is a new…

• 2 min read
Routing , high-speed , PCB design , Allegro PCB Editor , Why Move Up to 17.2

Breakfast Bytes

Optimizing Power with Palladium

At TSMC's OIP Ecosystem Symposium, Cadence's Frank Schirrmeister presented on Software…

• 4 min read
palladium z1 , Dynamic Power Analysis , TSMC , TSMC OIP , Incisive , power , Breakfast Bytes

Breakfast Bytes

What Is Automotive Tool Confidence Level 1?

ISO 26262 is the functional safety standard for automotive, as you probably already…

• 4 min read
tcl1 , tool confidence level , ISO 26262 , Breakfast Bytes , tcl

Breakfast Bytes

What's For Breakfast? Video Preview November 14th to 18th

https://youtu.be/OQ1c30nbD0s Monday: Red Hat's Jon Masters talks about ARM…

• less than a min read
Automotive , ARM Techcon , Jasper User Group , risc-v , NXP , jasper gold , JUG , formal , risc-v foundation , google , red hat , Jasper , open source , mobile , ISO 26262 , ARM , linux , Formal verification , verification

Breakfast Bytes

Moore and Medical at ARM TechCon

The second keynote on the first day of ARM TechCon was a double act with Greg Yeric…

• 7 min read
security , greg yeric , ARM Techcon , IoT , 28nm , 3nm , 5nm7nm , Mike Muller , medical , moore's law , privacy , ARM , Breakfast Bytes , 2nm

Whiteboard Wednesdays

Whiteboard Wednesdays - Industry Trends and Requirements for Autonomous Driving

In this week's Whiteboard Wednesdays video, the first in a three part series focusing…

• less than a min read
Automotive , Whiteboard Wednesdays , functional safety , automotive electronics

Breakfast Bytes

Who Wrote the Book on Formal Verification?

Who wrote the book on formal verification? Depending on whether you want to take…

• 5 min read
Intel , Jasper User Group , JUG , formal , CDC , Jasper , property checking , Equivalence Checking , jug 2016 , clock domain crossing , ARM , Breakfast Bytes , Formal verification , verification

Analog/Custom Design

Virtuoso Video Diary: I Am Not Promoting Layout Hierarchy Manipulation!

Are you contemplating manipulating your layout hierarchy by adding or removing a…

• 5 min read
Flatten , Transparent instances , Virtuoso Video Diary , Connectivity-driven , Make Cell , XL-compliance , Layout hierarchy manipulation , Custom IC Design , Virtuoso Layout Suite XL
CDNS - Fix Layout Hompage