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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Video: Incisive Formal Verifier R&D Leader Pradeep Goyal talks about Expert Formal…

Continuing the series that introduces you to the people that create the tools you…

• less than a min read
Pradeep Goyal , Joe Hupcey III , ABV , Functional Verification , Formal Analysis , Model-checking , formal , Incisive , assertions , Formal verification , IFV , verification , Assertion-based verification

Verification

High Level Synthesis for a Control-Dominated Design?

CDNLive! conferences are full of interesting and helpful presentations by customers…

• 1 min read
High-Level Synthesis , control-dominated , CDNLive , C to Silicon , Freescale , control , SystemC , CDNLive! , HLS , FPGA , System Design and Verification

Verification

Equine Anatomy, Pax Romana and the Reach of Standards

At the recent Synopsys EDA Interoperability Forum, the opening session focused on…

• 5 min read
pax romana , IP , markets , virtual platforms , TLM , horses , Acceleration , Standards , OSCI , Hogan , embedded software , Magarshack , Goodenough , system design , system , Accellera , Jim Hogan , SoC Realization , SystemC , interoperability , high level synthesis , ESL , architect , System Design and Verification

Verification

Early Holiday Present: Sudoku Solver Using Incisive Enterprise Verifier (IEV) and…

Allow me to interrupt the excellent "Meet R&D" series to share a small holiday present…

• 1 min read
ABV , Joerg Mueller , formal , simvision , Sudoku , ADS , PSL , IEV , Assertion-Driven Simulation , Formal verification

Analog/Custom Design

Improved IDF Tool Automatically Fixes Design Rule Violations in Virtuoso

Although many automatic layout generation tools are available to automate design…

• 6 min read
design rule violations , IC615 , analog , IC layout , IC 6.1.5 , Virtuoso , error correction , IDF , Custom IC Design , layout optimization , layout correction , interactive design fixing

Verification

Report on ARM Techcon 2011: Real and Virtual Software Apps, High-Speed Silicon and…

The acid test of any conference is how long the information and lessons learned linger…

• 4 min read
ARM Techcon , Charbax , Joe Hupcey III , Virtual System Platform , Richard Goering , 20nm , 14nm , EDA360 , VSP , YouTube , Lego , robot , Chi-Ping Hsu , ARM , Steve Leibson , Jason Andrews , Rubik's Cube

System, PCB, & Package Design 

What's Good About ... ? You'll Need to Open and See!

As we approach the Christmas season, many will reflect upon past Christmas times…

• 1 min read
PCB design , Christmas

Verification

Embracing Our Competitors with the Connections Program

In my last blog post , I described the Cadence Verification Alliance (VA) and how…

• 2 min read
NextOp , collaboration , Zocalo , Functional Verification , partnerships , VA , VIP , EDA360 , Duolog , verification alliance , Connections , interoperability , verification

Verification

Holiday Idea #1: Give the Gift of UVM Knowledge

Your favorite verification engineer has been good all year. Thousands of tests run…

• 2 min read
uvm , OVM , Incisive Enterprise Simulator , Accellera VIP TSC , UVM training , IES , IES-XL

System, PCB, & Package Design 

What's Good About AMS New PSpice Models? They’re in the 16.5 Release!

The 16.5 AMS library has a range of new models that can be used in diverse applications…

• 1 min read
AMS , AMS simulator , Allegro 16.5 , PSPICE , AMS simulation , SPB16.5 , library , Allegro

System, PCB, & Package Design 

Robert Hanson Tames the Topic of Power on Final Day of Cadence Event

On day-three of the Cadence Signal and Power Integrity Three Day Event, the audience…

• 1 min read
PCB , SI , PI , PDN , PCB Signal and power integrity , Robert Hanson , Power Integrity , Allegro 16.5 , IBIS-AMI , Power Delivery Network , Signal Integrity , OrCAD PCB SI , PCB Signal integrity , PCB design , PCI Express , DDR3 , Allegro

System, PCB, & Package Design 

Signal Integrity Education Continues at Cadence Event Featuring Robert Hanson

On day-two of the Cadence Signal and Power Integrity Three Day Event, it was standing…

• 1 min read
PCB SI , Robert Hanson , Allegro 16.5 , IBIS-AMI , TeamAllegro , Power Delivery Network , PDN Analysis , "PCB design" , OrCAD PCB SI , SPB16.5 , Allegro

Analog/Custom Design

Behavioral Model Validation with amsDmv

a msDmv (Analog Mixed Signal Design and Model Validation) is an application integrated…

• 4 min read
AMS , Mixed-Signal , analog behavoral , model validation , Virtuoso , behavioral models , mixed signal , amsDMV

System, PCB, & Package Design 

Scores of PCB Designers Gather for Free Signal Integrity Event

On day-one of the Cadence PCB Signal and Power Integrity Three-Day Even t, over 100…

• 2 min read
PCB , SI , PI , PDN , PCB Signal and power integrity , Robert Hanson , Power Integrity , Allegro 16.5 , IBIS-AMI , Signal Integrity , OrCAD PCB SI , PCB Signal integrity , PCI Express , DDR3 , Allegro

Verification

Secrets of the (Verification) Alliance

In a recent post , I discussed the need for cross-vendor cooperation in EDA, especially…

• 3 min read
uvm , collaboration , Specman , Functional Verification , VAalliance , partnerships , VA , VIP , EDA360 , EDA , Verisity , verification alliance , Doulos , AMIQ , Oski , verification

Verification

Video: Meet Incisive Enterprise Verifier R&D Architect Vinaya Singh

Continuing the series of introducing you to the people that create the tools you…

• less than a min read
Joe Hupcey III , ABV , Vinaya Singh , Functional Verification , Formal Analysis , formal , video , assertions , IEV , Assertion-Driven Simulation , Formal verification , Assertion-based verification

System, PCB, & Package Design 

What's Good About Graphical Operation Locking in Capture? You Can Easily Do This…

A schematic page often contains a large number of different types of objects like…

• 8 min read
"capture CIS" , Design Entry CIS , OrCAD Capture , Capture CIS , Capture-CIS , Allegro 16.5 , SPB , design , OrCAD , Design Reuse , Design Entry , SPB16.5 , PCB Capture , Schematic , operation locking

Verification

Update to the OVM Register Package

OVM users have something new to give thanks for this holiday season -- an update…

• 2 min read
uvm , IP-XACT , Functional Verification , OVM , Register Package , Incisive , IES , OVMWorld , verification

Analog/Custom Design

Cadence is the OpenText Connectivity Partner of the Year

Cadence is pleased to be honored by the OpenText Global Partners Program as their…

• less than a min read
ExceedOn Demand , OpenText , Exceed on Demand , remote access , analog , connectivity partner , Open Text , Virtuoso , Custom IC Design
CDNS - Fix Layout Hompage