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Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Artificial Intelligence (AI)

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design
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Blog - Post List
Latest blogs

Digital Design

Five-Minute Tutorial: ecoAddRepeater

In today's tutorial, we're going to talk about the Encounter Digital Implementation…

• 3 min read
EDI system , tutorial , encounter , Digital Implementation , five minute , ecoAddRepeater

SoC and IP

Angelbird Ltd. Introduces “Wings,” a low-cost PCIe SSD for PCs. $239 for 16 Gbyt…

Stop me if you’ve heard this one. The fastest way to get high performance from an…

• less than a min read

SoC and IP

Hitachi-LG Data Storage fixes optical drive with SSD assist to use one SATA port

Hitachi-LG Data Storage has updated the hybrid optical/SSD drive it announced earlier…

• less than a min read

SoC and IP

Made in South Korea: Graphene memristor memory cells on a flexible plastic subst…

IEEE Spectrum has just reported on the successful fabrication of graphene-based memory…

• 1 min read

SoC and IP

Brian Fuller @EETimes: Renesas to put MRAM in 90nm microcontrollers by 2013

EETimes’ Brian Fuller is blogging live from the Renesas DevCon down in southern California…

• 1 min read

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Customizable Datatips? Look to SPB16.3 and See

In pre-select mode Allegro displays a datatip that provides information about the…

• 5 min read
PCB , PCB Layout and routing , SPB16.3 , Allegro 16.3 , SPB 16.3 , property , PCB Editor , PCB design , Allegro PCB Editor , PCB Capture , Allegro

Digital Design

3D-IC TSV Realization: The Race Has Begun!

3D IC discussions are creating quite a buzz these days. No conference is complete…

• 3 min read
packaging , 3D-IC , 3DIC , TSV , Floorplanning , Test , Digital Implementation , 3D , thermal

Verification

Connections Partner NextOp on Assertion Synthesis and Assertion-Based Verification…

As anyone working in Formal and Assertion-Based Verification (ABV) knows, the task…

• 1 min read
Cadence Connections , NextOp , ABV , CDNLive , Functional Verification , formal , EDA360 , assertion synthesis , IEV , IFV

SoC and IP

Sandforce Enterprise-Class SSD 2500/2600 processors deliver double performance

SandForce has just announced a new enterprise-class SF-2000 SSD processor family…

• less than a min read

Verification

Video: Interview With NextOp CEO Yunshan Zhu on Assertion-Based Verification (ABV…

What makes a startup "hot"? To be sure, trade press and blogger attention helps.…

• 1 min read
Cadence Connections , NextOp , DAC , ABV , CDNLive , Functional Verification , Formal Analysis , formal , EDA360

SoC and IP

Anandtech reports that Intel’s new SSDs that incorporate 25nm Flash will have 4x…

This blog previously reported that Intel will be rolling out new versions of its…

• less than a min read

Verification

"We Want UVM 1.0! When Do We Want it? Now!"

Short of holding signs and yelling slogans, the 12 customers I visited in the past…

• 3 min read
SystemVerilog , uvm , OVM ML , OVM , VIP , OVM e , EDA360 , Incisive , OVM SV , AMIQ , Accellera VIP TSC , IES , VMM , IES-XL

Analog/Custom Design

Things You Didn't Know About Virtuoso: ADE XL--Take This Job and...Run It!

Sometimes these articles just write themselves... Last week, 3 different people asked…

• 3 min read
Analog Simulation , analog , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

System, PCB, & Package Design 

What's Good About AMS Simulator Fonts, Models, and More? It's in SPB16.3!

The SPB16.3 release of the Allegro AMS Simulator environment contains a few additional…

• 2 min read
SPB16.3 , AMS , AMS simulator , SPB 16.3 , PSPICE , SPB , AMS simulation , Design Entry , library

RF Engineering

Measure Twice, Cut Once for Transistor ft

Recently there was an inquiry about the methodology for performing the f t (transition…

• 3 min read
RF , Ft , ADE-L , Analog Simulation , Measuring Transistor ft , transistor , Analysis , ADE , Virtuoso , parametric , sweep

Verification

Why EDA Verification is Like Pro Sports

First, I would like to introduce myself. My name is Jim Kjellsen. I've recently joined…

• 2 min read
Functional Verification , football , pro sports , sports , Kjellsen , verification

SoC and IP

Renesas introduces new 1.1Gbit low-latency DDR DRAM (LLDRAM) for networking apps

Renesas has introduced a new 1.1Gbit, low-latency DDR DRAM (LLDRAM) primarily for…

• 1 min read

Verification

Tech Tip: Distributing Incisive Enterprise Verifier (IEV) Engines and Assertions…

A common problem when distributing engines and assertions in Incisive Enterprise…

• 1 min read
ABV , Functional Verification , Formal Analysis , formal , LSF , Enterprise Manager , IEV

SoC and IP

OCZ invents proprietary 20Gbps link for SSDs, snubbing SAS, SATA, and PCIe

Yesterday, OCZ released a curious statement saying that it was unveiling a proprietary…

• less than a min read
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