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Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

Favorite Features Of An IC Package Designer: Assembly Rule Checks

This is the third in a series of discussions we would like to open up regarding…

• 1 min read
SPB16.3 , package , SiP , Analog and RF SiP design , Digital SiP design , 3D-IC , Allegro 16.3 , IC Packaging and SiP , IC Packaging & SiP design , SPB , wirebond profile library , IC Package Physical layout and co-design , Kulicke & Soffa

System, PCB, & Package Design 

What's Good About Allegro GRE Bundle Editing? SPB16.3 Has Many New Enhancements!

The Allegro Global Route Environment (GRE) has expanded its capabilities in the area…

• 4 min read
PCB , PCB Layout and routing , SPB16.3 , global route , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Layout , PCB design , Allegro PCB Editor , GRE , Allegro

Analog/Custom Design

Things You Didn't Know About Virtuoso: ADE XL

I know, it's been a long time since my last post. You see, we've finally arrived…

• 5 min read
IC 6.1 , ADE , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

SoC and IP

Pasadena SSD Maker Foremay crams 2Tbytes into 3.5-inch SSD, 1Tbyte into 2.5-inch…

Foremay’s EC188 M-series Model-V SSDs is now available in a 2-Tbyte version for 3…

• less than a min read

Digital Design

Programmatically Capturing Cell Delay In The Encounter Digital Implementation Sy…

A while back we were talking about how to programatically troubleshoot timing violations…

• 5 min read
Static timing analysis , CTE-TCL , Digital Implementation , scripting , tcl

SoC and IP

Micron provides detailed synopses of its NAND Flash and PCM presentations at Flash…

Micron has done a very smart thing (note to marketers: take matters into your own…

• 5 min read

SoC and IP

MemCon 2010: DDR3 1GHz and Beyond--Preregistered attendance now approaching 800.…

Yesterday, preregistration attendance for MemCon 2010 jumped the 600 threshold. Today…

• less than a min read

SoC and IP

Add PNY to the growing list of memory module vendors entering the SSD fray

Memory-module vendor PNY has just announced its Optima line of 2.5-inch SSDs with…

• less than a min read

Verification

Video Interview: UVM Book Authors Sharon Rosenberg And Kathleen Meade

Earlier today a new book called "A Practical Guide to Adopting the Universal Verification…

• 1 min read
DAC , uvm , Functional Verification , OVM , DVcon , eRM , Accellera VIP TSC , VMM

SoC and IP

One Week Left: MemCon registration zooms past 600 attendees. Theme: DDR3 - 1 GHz…

You have only one more week to sign up for MemCon 2010! It’s the one day this year…

• 1 min read

Verification

System Realization Alliance -- An Industry Collaboration

System Realization is a very broad topic. It encompasses all aspects of system design…

• 1 min read
TLM , system realization , EDA360 , HLS , ESL , verification

Verification

New UVM Book Is For You And U But Not Ewe

A Practical Guide to Adopting the Universal Verification Methodology (UVM) is the…

• 2 min read
SystemVerilog , uvm , TLM , Functional Verification , Testbench simulation , OVM , EDA360 , Register Package , OOP , Accellera , eRM , Accellera VIP TSC , IES-XL

SoC and IP

Wondering about mobile and consumer design and SPMT memory? Here’s your chance to…

This blog has discussed an up-and-coming serial memory-interface technology called…

• less than a min read

SoC and IP

Intel X-25M 80GB SSD Performance after 45 days of use: Time ain’t on my side, no…

A member of Overclock.Net going by the handle Kiggold just posted two screen shots…

• less than a min read

SoC and IP

DDR3 power savings may be more important for Embedded Apps than for PCs

A new hands-on article written by Patrick Schmid and Achim Roos just appeared on…

• 2 min read

Verification

Sign Up For Free Verification Sessions -- Only A Few Days Left

Mark your calendar and sign up for the two upcoming free verification sessions sponsored…

• 1 min read
workshops , Specman , Coverage-Driven Verification , EDA , Incisive , e , team specman , Aspect Oriented Programming , MDV , IES-XL

Verification

Software Development Tool Teardown For The Motorola Droid

Lately, device teardowns of consumer electronics have become popular. There are many…

• 4 min read
ADB , GDB , android , QXDM , DDMS , JTAG , ETM , vnc , Monkey , QPST , Systemm Verification

Verification

More Thoughts On How To Choose Between The OVM And The UVM

There has been a lot of on-line discussion since DAC about whether the Universal…

• 2 min read
uvm , OVM , VIP , EDA , Accellera , Mentor

SoC and IP

AnandTech analyzes Crucial C300 SSD with Marvell controller in “The SSD Diaries.…

Anand Lal Shimpi, the man behind the AnandTech.com Web site, has published an extended…

• less than a min read
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