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Cadence Japan

【ホンダHGR＋ケイデンス前編】Physical AIの“Physical”とは何か─現実に勝てないAIは、動けない

※本記事は小川厚 氏（Honda総合研究センター）の執筆、ケイデンス監修によるものです。 皆さん、こんにちは。HGRセンター長の小川厚（おがわ あつし）です…

Cadence Japan
• less than a min read
featured , japanese blog

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

Verification

What Does EDA360 Mean for Verification Engineers?

I trust that most of you have seen the recent flurry of blog posts and articles about…

• 2 min read
uvm , IP , Verification methodology , OVM , VIP , EDA360

Verification

System Realization activities at CDNLive! EMEA this week

CDNLive! EMEA will be held in Munich again this year, and there’s lots of news about…

• 2 min read
System Design and Verification , cdnLive! system realization

SoC and IP

Magnetic nanodot materials breakthrough presages high-density MRAM--possible competition…

From North Carolina State University (NCSU) comes news of a materials breakthrough…

• 1 min read

SoC and IP

More free DAC exhibit tix; One more chance to win an Apple iPad

A bit more than a week ago, this blog carried the news that you could get a free…

• 1 min read

SoC and IP

Samsung announces imminent release of a multichip module integrating DRAM and PCM…

Hot on the heels of Numonyx’ announcement of two commercial PCM (phase-change memory…

• 1 min read

Verification

See You at CDNLive! EMEA

Today, Team Specman reported that next week's CDNLive! is shaping up to be a big…

• 2 min read
CDNLive!ive! , System Design and Verification

Verification

2010 CDNLive Munich Guide for Specmaniacs

Good news for Specmaniacs based in the EU: next week from May 4-6 is the annual CDNLive…

• 2 min read
Specman , CDNLive , Functional Verification , Cadence VIP portfolio , OVM , OVM e , e , Mike Stellfox , techtorial

Verification

Team Verify's 2010 CDNLive Munich Guide

We're excited to report that next week's annual CDNLive! event in Munich will feature…

• 1 min read
ABV , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Contributions , SVA , PSL , MDV , IEV , IFV

System, PCB, & Package Design 

What's Good About APD’s Super Smooth Routing? See for yourself in the SPB16.3 Release

When using the point-to-point routing in the packaging products ( APD and SIP ),…

• 3 min read
PCB , PCB Layout and routing , IC Packaging and SiP Design , IC Packaging , Allegro 16.3 , SPB 16.3 , APD , advanced package designer , PCB design , Allegro PCB Editor , Cline change

Verification

Harris-Cadence-Mathworks-Xilinx Success Cuts Verification Time 85%

More and more often it takes a village to achieve verification success. As reported…

• 1 min read
Functional Verification , Incisive , xilinx , IES , FPGA , Matlab , IES-XL

SoC and IP

NAND Flash as the media killer: Sony to kill the floppy in Japan, finally

Sometimes it takes decades but NAND Flash semiconductor memory is turning out to…

• 1 min read

System, PCB, & Package Design 

Favorite Features of an IC Package Designer: Flexible 3D Viewing

This is the first in a series of discussions we would like to open up regarding…

• 1 min read
SiP , Digital SiP design , 3D-IC , Allegro 16.3 , TSV , APD , IC Packaging & SiP design , IC Package Physical layout and co-design , Kulicke & Soffa

Verification

Verified by e/Specman: The Palladium XP Verification Computing Platform

After much anticipation, it feels great to be free to proclaim that e /Specman (as…

• less than a min read
metric driven verification (MDV) , Functional Verification , e , Palladium XP , MDV , IES-XL

SoC and IP

Corsair Video vividly shows SSD speedup on laptop

Wondering whether an SSD really makes that much difference to laptop performance…

• less than a min read

Digital Design

Hands Up, Anyone Believe That Toyota's Problems Are All Physical?

In the past number of weeks/months we have all seen how Toyota has struggled to manage…

• 2 min read
toyota , Digital Implementation , BMW , microprocessor , verification

Verification

Ubuntu on ARM is Growing

Based on the title, you probably guessed I'm talking about growing in popularity…

• 6 min read
virtual platform , System Design & Verification , Embedded Linux , QEMU

System, PCB, & Package Design 

Who’s up for Chinese?

Recently, someone asked me " .. . why bother translating OrCAD products to Chinese…

• 1 min read
Capture CIS' , PSPICE , OrCAD , PCB design , PCB Capture , Schematic

SoC and IP

What is a Flash cache?

A Flash cache acts like SRAM memory caches that are designed to speed up DRAM access…

• 3 min read

SoC and IP

Free DAC Tix -- Better hurry ‘cause they’re going fast

Love DAC? Design chips? Looking for a job? Today’s your lucky day. Denali, Atrenta…

• 1 min read
CDNS - Fix Layout Hompage