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Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis
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Blog - Post List
Latest blogs

Digital Design

Encounter Digital Implementation System 8.1 San Jose Live Blog

I'll be live blogging from the Cadence Campus in San Jose today. We're doing a seminar…

• less than a min read
Low Power , encounter , Digital Implementation , mixed signal , design closure , Encounter Digital Implementation System 8.1

Verification

Tracing TLM 2.0 Activity in an ESL Design – Part 2

In my last post I discussed two ad hoc approaches for tracing TLM 2.0 activity in…

• 4 min read
System Design and Verification , TLM 2.0 , George Frazier , SystemC , TLM 2.0 Trace

Verification

Another New Blog About the e Language

We are compelled to briefly interrupt Efrat's excellent series on Performance-Aware…

• less than a min read
IEEE 1647 , Specman , Functional Verification , e , OVMWorld

Verification

Verification of AUTOSAR Software Using a SystemC Virtual Platform

[Please welcome ISX R&D team member Markus Winterholer back to the Team ESL blog…

• 2 min read
AUTOSAR , BSW , System Design and Verification , RTE , SystemC , VFB , ISX

Verification

ESC and "Booth-Centric" vs. "Paper Centric" Shows

Last Wednesday I walked the floor of the Embedded Systems Conference (ESC) , with…

• 2 min read
events , DAC , CDNLive , Functional Verification , ESC , DVcon

Verification

Performance-Aware e Coding Guidelines – Part 2

Building on Part 1 where I talked about the “do’s and don’ts” of List performance…

• 2 min read
performance , IntelliGen , Specman , Functional Verification , tech tips , OVM e , e , OVM-e , specman elite , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Analog/Custom Design

Virtuoso, the SATs, and the Dark Knight - Part II

Well, are you still wondering what Virtuoso has to do with the SATs and The Dark…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

Observations From the Embedded Systems Conference

Yes, there was another Embedded Systems Conference this year. Several "multi-year…

• 2 min read
Embedded Systems Conference , RTL , System Design and Verification , ESL

Verification

EDN's 19th Annual Innovation Awards

Two of Cadence system D&V products have been selected as the finalists for the EDN…

• 1 min read
System Design and Verification , Palladium , EDN , dpa , C-to-Silicon Compiler

Verification

C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

Some customers have inquired if C-to-Silicon Compiler (CtoS) is a “Low Level” Synthesis…

• 1 min read
High-Level Synthesis , CTOS , TLM , high-level synthesis adoption , RTL , System Design and Verification , TLM 2.0 , C-to-Silicon , SystemC , C-to-Silicon Compiler , ESL , architect

Analog/Custom Design

Connectivity and Constraint Driven Design: Will It Ever Become The Standard for Custom…

In the late 70's and early 80's system level PCB and Digital IC physical design evolved…

• 6 min read
VSR , Virtuoso IC 6.1.3 , Virtuoso Custom Placer , CAD , IC 6.1.4 , Custom IC Design , custom design technology , VCP

System, PCB, & Package Design 

What's Good About Schematic Drawing Standards?

This past week, there has been a very interesting discussion on the "icu-pcb-forum…

• 2 min read
PTF , PCB design , Schematic , Allegro

Verification

Is ESL changing EDA? Absolutely!

Geoffrey James's recent article provides a succinct description of several important…

• less than a min read
DAC , Estimation Planning , TLM , RTL , System Design and Verification , Synthesis , ESL

Verification

Performance-Aware e Coding Guidelines - Part 1

[Team Specman welcomes back Methodology R&D leader Efrat Shneydor to present a 5…

• 1 min read
IEEE 1647 , performance , IntelliGen , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Welcome to Richard Goering

Let me be among the first in the Cadence "blogger corps" to welcome Richard Goering…

• less than a min read
Industry Insights , Functional Verification , EDA

Analog/Custom Design

What’s all the Hoopla with PDKs?

At a purely technical level, Process Design Kits are fairly innocuous. They are used…

• 2 min read
IC 6.1 , Virtuoso , PDK , Custom IC Design , Process Design Kit

Analog/Custom Design

Analog Design Validation: What is Your Recipe for Success?

Every analog circuit design goes through some kind of electrical validation step…

• 2 min read
Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

SoC and IP

DRAMs: Historically, how bad is this downturn?

DRAMs: Another look at how bad it is: Last week, we (finally) published our summary…

• 3 min read

Verification

Software Verification or Validation With ISX?

[Please welcome Markus Winterholer to the Team ESL blog. Markus is one of the founding…

• 2 min read
validation , embedded world conference , System Design and Verification , ISX , ARM , verification
CDNS - Fix Layout Hompage