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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Cadence Certified on TSMC N3, Ultralink on N6, and 3DFabric

Yesterday was it TSMC Technology Symposium. Normally this would have been held face…

• 3 min read
n5 , CoWoS , n3 , TSMC , TSMC Technology Symposium , InFO , n7 , n6 , d2d , n16 , n28

Analog/Custom Design

Virtuoso Meets Maxwell: Unified Libraries — Making Way For Cross-Platform Flows

Heterogeneous integration of components using different process technologies can…

• 6 min read
Technology Independent Layout Pcell , ICADVM18.1 , Unified Library , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF , Cadence SiP Layout , TILP , Custom IC Design , VMM

Breakfast Bytes

Under the Hood of Xcelium ML

At the recent CadenceLIVE Americas, Yosinori (Yoshi) Watanabe presented what he titled…

• 5 min read
featured , xcelium ml , machine learning , xcelium , simulation

Breakfast Bytes

Sunday Brunch Video for 23rd August 2020

https://youtu.be/LIKlevqCB-U Made in front of my TV (camera Carey Guo) Monday: Alberto…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

Sigrity Aurora：融合Allegro用户体验与Sigrity强大功能，为工程师提供设计同步分析

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者 Paul McLellan 文章 “ Sigrity Aurora: In-Design…

• less than a min read
阻抗分析 , SI , IDA , PI , Chinese blog , 电源完整性 , Sigrity Aurora , IBIS , 并行设计 , in-design analysis , Aurora , 中文 , 耦合 , 设计同步分析 , Sigrity , 压降分析 , 信号完整性 , Allegro

Academic Network

Custom IC, Analog, and RF Design Training Deep Dive: Part 4

Welcome to the fourth and final part of the Custom IC, Analog, and RF Design Online…

• 4 min read
Europractice , Cadence Academic Network , CMC Microsystems , online training

Digital Design

Pegasus Verification System Product Page is Live!!!

We are excited to share that PegasusTM Verification System Product page is now live…

• 1 min read
Pegasus Verification System , Physical verification , verification signoff solution , pegasus , DRC , PVS

Breakfast Bytes

Anirudh's Keynote: A New Product...and an Acquisition

Anirudh Devgan, Cadence's President, gave the keynote to open the second day of CadenceLIVE…

• 3 min read
cadencelive 2020 , cadencelive americas , Anirudh Devgan , cadencelive

System, PCB, & Package Design 

2019 HF2 Release for Clarity, Celsius, and Sigrity Tools Now Available

The 2019 HF2 production release for Clarity, Celsius, and Sigrity tools is now available…

• 8 min read
Sigrity 2019 HF2 , Celsius Thermal Solver , Speed2000 , Sink Voltage , Sigrity PowerDC , Clarity 3D Solver , PowerDC

Analog/Custom Design

Virtuosity: What's New in Run Plan - Part IV

Click here to view our latest blog in the What's New in Run Plan blog series that…

• 4 min read
Virtuoso Analog Design Environment , Virtuoso , Virtuosity , Run Plan , Custom IC Design , Custom IC , IC6.1.8 , Assembler , ADE Assembler

Breakfast Bytes

HOT CHIPS: Scaling out Deep Learning Training

The annual HOT CHIPS conference took place on August 17-18. Of course, it was virtual…

• 10 min read
deep learning , scaling , NVIDIA , parallelism

Analog/Custom Design

Virtuoso Video Diary: The SKILLed Way of Using Plotting Templates

Read through this blog to know more about how to use the maeGetAllPlottingTemplates…

• 3 min read
Cadence blogs , ICADVM18.1 , ADE Explorer , maestro , plotting , Virtuoso Visualization and Analysis XL , Virtuoso Analog Design Environment , Virtuoso , plotting templates , Virtuoso Video Diary , maestro plotting templates , Custom IC Design , SKILL APIs , IC6.1.8 , SKILL , ADE Assembler

System, PCB, & Package Design 

BoardSurfers: Training Insights: How to Run a RAVEL Rule from the GUI

With the current scenario of COVID-19, you cannot do without rules. You have to soak…

• 3 min read
17.4 , 17.4-2019 , PCB design , Allegro PCB Editor

Breakfast Bytes

Thermal Analysis of Protium X1

There's a phrase in software development "eat your own dogfood". In fact, there's…

• 4 min read
celsius , Protium , FPGA prototyping , thermal

Analog/Custom Design

Virtuoso IC6.1.8 ISR13 and ICADVM18.1 ISR13 Now Available

The IC6.1.8 ISR13 and ICADVM18.1 ISR13 production releases are now available for…

• 3 min read
Cadence blogs , ICADVM18.1 , ADE Explorer , EM Solver , Virtuoso Layout EXL , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso , IC Release Blog , Custom IC Design , Virtuoso Layout Suite , Custom IC , ADE Verifier , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL

System, PCB, & Package Design 

IC Packagers: Designing a Package from the Flip-Chip’s Perspective

Most package substrates are designed as they will be placed onto the host PCB if…

• 6 min read
Allegro X Advanced Package Designer

Breakfast Bytes

Climbing Annapurna to the Clouds

One of the keynotes at last week's CadenceLIVE Americas 2020 was by Nafea Bshara…

• 4 min read
nitro , EDA , cloud , annapurna , aws , cadence cloud , gravitron

カスタムIC／ミックスシグナル

Virtuosity: 古いADEのstateやviewをADE ExplorerまたはADE Assemblerで開く

Virtuoso ® ADE L stateやVirtuoso ® ADE XL viewを開くとき、デフォルトのアプリケーションが、以前の古いADE LまたはXLにセットされていることが面倒だと感じた事はありませんか…

• less than a min read
Explorer , ADE Migration , ADE , Virtuoso Analog Design Environment , Virtuosity , IC6.1.7 , japanese blog , Custom IC Design , Assembler

Breakfast Bytes

Alberto's Keynote: Cadence and Academia

On the last day of CadenceLIVE 2020, there was a keynote by Alberto Sangiovanni-Vincentelli…

• 4 min read
Berkeley , Alberto Sangiovanni-Vincentelli
CDNS - Fix Layout Hompage