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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Verification

Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 2…

Welcome back to this account of the IP Security Panel at the Accellera Luncheon at…

• 6 min read
security , luncheon , DAC 2019 , Panel , Accellera

System, PCB, & Package Design 

IC Packagers: The Spaces Between Your Dies

Die stacks are starting to look more like skyscrapers every year. If your packages…

• 4 min read
IC Packaging , APD , SiP Layout

Breakfast Bytes

12% Is Not Enough: Women in Engineering

At CDNLive EMEA, there was a Women's track and the first presentation was by Elizabeth…

• 4 min read
women's engineering society , STEM , CDNLive , CDNLive EMEA

System, PCB, & Package Design 

BoardSurfers - Aerials and Bails: Take a Walk on the Wild Side...with Auto-Roami…

We have had this question before, so it’s a good one to remind everyone of in case…

• 2 min read
APD , PCB Editor , SiP Layout

Life at Cadence

Cadence: A Great Place to Work—Asia

For the first time ever, Great Place to Work ranked Cadence as the #15 Best Place…

FormerMember • 5 min read
Community , giving back , GPTW , great place to work

Academic Network

International Symposium on Physical Design 2019

The International Symposium on Physical Design (ISPD) contest is a well-known competition…

• 4 min read
ISPD , Academic Network , Innovus , ISPD 2019 Contest

Breakfast Bytes

Intel and PSS...and Simics, a Blast from My Past

One of the newest standards in verification is PSS, the Portable Stimulus Standard…

• 4 min read
Intel , DAC , Perspec , pss , portable stimulus standard

Verification

Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 1…

Figure 1: The panel and crowd Citizens—the tech world is in trouble. With the ever…

• 5 min read
security , luncheon , DAC 2019 , Panel , Accellera

Breakfast Bytes

Sunday Brunch Video for 23rd June 2019

https://youtu.be/6GUoDQkSoLY Made at Paris Air Show (camera Simon Fielding) Monday…

• less than a min read
sunday brunch

Breakfast Bytes

Why Is 5G Such a Big Deal?

Yesterday was my post What Is 5G? which is the first half of my introductory look…

• 7 min read
5G , mmwave , mobile

System, PCB, & Package Design 

IC Packagers: Constructing Components from Manufacturing Data

We’ve all been there. The only (or most accurate) data that we have for a component…

• 5 min read
IC Packaging and SiP , APD , SiP Layout

System, PCB, & Package Design 

BoardSurfers - Aerials and Bails: How to Split a Viastack

Today’s compact and powerful devices require small and high-density PCBs. Tight routing…

• 2 min read
APD , PCB Editor , SiP Layout , Allegro

Breakfast Bytes

What Is 5G?

At the DAC theater, Cadence's Ian Dennison talked about 5G Intelligent System Design…

• 7 min read
5G , mmwave , IoT , mobile

Verification

Master of ‘e’? Now You Can Prove It!

The knowledge and experience of using Specman/ e tells everyone that you have acquired…

• 1 min read
Specman , Specman/e , Specman e , badge , e , e language , specman elite

Digital Design

Exploring AI / Machine Learning Implementations with Stratus HLS

A lot of AI design is done in software and, while much of it will remain there, increasing…

• 4 min read
High-Level Synthesis , TensorFlow , machine learning , Stratus , SystemC , HLS , AI

Breakfast Bytes

Assessing Bias in Computer Vision Systems

I came across a fascinating document from Facebook on methods to assess bias in computer…

• 5 min read
imagenet , Computer Vision , Facebook , convolutional neural networks , neural networks , bias

Whiteboard Wednesdays

Whiteboard Wednesdays - Passport Partners Program Expands Customer Cloud Deployment…

In this week's Whiteboard Wednesdays video, Craig Johnson explains the purpose of…

• less than a min read
Whiteboard Wednesdays , Cloud Passport , Cloud-based Design , cadence cloud

Breakfast Bytes

DAC: The View from Wall Street

Jay Vleeschhouwer did his annual...well, he did it last year, too...View from Wall…

• 4 min read
DAC , wall street , vleeschhouweer

Analog/Custom Design

Virtuoso IC6.1.8 ISR4 and ICADVM18.1 ISR4 Now Available

The IC6.1.8 ISR4 and ICADVM18.1 ISR4 production releases are now available for download…

• 4 min read
ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , Interactive and Assisted Routing , Virtuoso RF , ADE , Virtuoso Analog Design Environment , Layout , Virtuoso , cadenceblogs , IC Release Blog , New in EDA , Custom IC Design , Virtuoso Layout Suite , Custom IC , IC6.1.8
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