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Academic Network

ECE Master Students of Duke Kunshan University Visited Cadence Shanghai Office

The Cadence Academic Network was very excited to host students from Duke Kunshan…

Tracy Zhu 6 Nov 2019 • 2 min read

university , Cadence Academic Network , university program

Analog/Custom Design

Virtuoso Video Diary: Click – Take a Snapshot – Smile!

This blog talks about about the Snapshots feature introduced in ADE Verifier in IC6…

Rashmi G 6 Nov 2019 • 4 min read

verifier , Analog Design Environment , ICADVM18.1 , Functional Verification , Formalized Verification , snapshots , ADE Verifier Snapshots , ADE , Mixed-Signal , Virtuoso , cadenceblogs , Virtuoso Video Diary , Custom IC Design , ADE Verifier , IC6.1.8 , Verifier new feature , verification

Breakfast Bytes

Tempus Power Integrity Solution

One of the challenges in leading-edge nodes today is the resistivity of the interconnect…

Paul McLellan 6 Nov 2019 • 3 min read

Tempus , Voltus , signoff

Verification

Specman: Analyze Your Coverage with Python

In the former blog about Python and Specman: Specman: Python Is here! , we described…

teamspecman 6 Nov 2019 • 8 min read

Specman , Specman coverage engine , coverage , Python , Functional Verification , Specman e , e , e language , specman elite , functional coverage

System, PCB, & Package Design

IC Packagers: Scripting Updates in 17.4

If you joined us last week to see the visual changes to be expected when you download…

Tyler 6 Nov 2019 • 5 min read

APD , PCB Editor

Computational Fluid Dynamics

ArianeGroup: Optimization of the Liquid Hydrogen Turbopump of the Vulcain Rocket…

ArianeGroup is the world’s leading designer and manufacturer of rocket launchers…

AnneMarie CFD 5 Nov 2019 • 2 min read

CFD , NUMECA

Breakfast Bytes

Dead Ends

Sometimes something comes along that looks like it is a portent of things to come…

Paul McLellan 5 Nov 2019 • 7 min read

Automotive , Breakfast Bytes

System, PCB, & Package Design

Cadence OrCAD and Allegro 17.4-2019 is Now Available

Here is a sleeker and more modern version of the OrCAD and Allegro release, with…

AllegroReleaseTeam 4 Nov 2019 • 4 min read

Library Creator , System Capture , 17.4 , IC Packaging , OrCAD Capture , APD , PSPICE , PCB Editor , Constraint Manager , Topology Explorer

The India Circuit

Is Design in India on the Upswing?

The India Electronics and Semiconductor Association (IESA) recently organized a two…

Madhavi Rao 4 Nov 2019 • 2 min read

IESA , make in india , Design In India

Breakfast Bytes

IEDM 2019 Preview

Coming up in the beginning of December is the 65th International Electron Devices…

Paul McLellan 4 Nov 2019 • 6 min read

IEDM

Computational Fluid Dynamics

Creacoustic: Transmission Loss Simulation of Reactive and Dissipative Creacoustic…

Silencers and industrial mufflers are used to limit noise emissions in applications…

AnneMarie CFD 3 Nov 2019 • 1 min read

PCB、IC封装：设计与仿真分析

CDNLive China 2019 现场精彩回顾及演讲资料下载

本文翻译节选自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章“ CDNLive China 2019 “。 space…

SDA China 1 Nov 2019 • 1 min read

Chinese blog , CDNLive , 中文 , CDNLive China 2019 , 智能系统设计 , Clarity 3D Solver

Breakfast Bytes

Computational Hardware

This is the second part of a three-part series of posts on computation. The first…

Paul McLellan 1 Nov 2019 • 4 min read

computational software , computation

Analog/Custom Design

Virtuoso Video Diary: schTraceNet, a Simple Solution to Complex Questions!

Take probing nets to the next level, define a callback based on the SKILL schTraceNet…

sarahfino 31 Oct 2019 • 2 min read

schTraceNet , Virtuoso Schematic Editor , ICADVM18.1 , Net Tracing , video , tracing a net , Virtuoso , Schematic Editor , Virtuoso Video Diary , Probing , Circuit Design , Probes assistant , Custom IC Design , Custom IC , IC6.1.8 , Schematic , net area

System, PCB, & Package Design

Sigrity 2019 Release Now Available

The Sigrity 2019 production release is now available for download.

SigrityReleaseTeam 31 Oct 2019 • 3 min read

Celsius Thermal Solver , OptimizePI , Sigrity 2019 release , Clarity 3D Solver , XtractIM , PowerDC , PowerSI

Breakfast Bytes

Computation and the Data Explosion

Everywhere you look these days, you get told that there is a data explosion going…

Paul McLellan 31 Oct 2019 • 6 min read

computational software , computation

定制IC芯片设计

Virtuosity: Automated Device Placement和Routing - Grid生成

该博客是“Automated Device-Level Placement和Routing ”系列的第三个博客，着重强调了遵循网格化的布局和布线方法的重要性。您将看到automated…

Sravasti 31 Oct 2019 • 1 min read

Chinese blog , Cadence blogs , Automated Device Placement , ICADVM18.1 , Automated Device-Level Placement , automation , Automatic Placement , Advanced Node , Auto Device P&R , Layout EXL , APR , Auto P&R , Virtuoso , Virtuosity , Virtuoso Placement , New in EDA , Custom IC Design , Custom IC

System, PCB, & Package Design

IC Packagers: Welcome to 17.4!

It’s here! Less than two weeks ago, on October 18, 2019, Cadence released the 17…

Tyler 30 Oct 2019 • 6 min read

17.4 , APD

Breakfast Bytes

Implementing Automotive Radar on Tensilica Processors

The big controversy about sensors in autonomous driving is whether lidar is essential…

Paul McLellan 30 Oct 2019 • 4 min read

Automotive , radar , fmcw , ADAS

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