Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

CASPA Fuses AI and Semiconductor

CASPA is the Chinese American Semiconductor Professional Association. Once a year…

• 9 min read
deep learning , semi , caspa , Semiconductor , AI

Academic Network

Cadence Academic Network Lead Institutions

Introduction Many suggestions were spinning around the globe, many ideas are being…

• 3 min read
university , Academic Network

The India Circuit

Would You Let Your Child Ride in an Autonomous Car?

DVCon is one of the premier conferences WW for design and verification. The DVCon…

• 3 min read
DVCon India , DVcon , ADAS , autonomous vehicles

Analog/Custom Design

Dealing with AOCVs in SRAMs

Systems on Chip, or SoCs as they’re more commonly called, have become increasingly…

• 4 min read
legato , custom/analog , Monte Carlo analysis , Monte Carlo , Spectre , Custom IC Design , Custom IC

Breakfast Bytes

Foundry Roadmaps: Intel, Samsung

I definitely had cognitive dissonance at the ARM foundry talks at TechCon. The first…

• 6 min read
Intel , ARM Techcon , Samsung , TSMC , icf , FinFET , 7nm , ARM , EUV , Techcon , FD-SOI

Verification

Slaying the Gate-Level Simulation (GLS) Dragon: Your Knight Is Here!

Even today, gate-level simulation is still a major signoff step for most semiconductor…

• 2 min read
app note , Functional Verification , GLS

Breakfast Bytes

What's For Breakfast? Video Preview November 20th to 22nd 2017

https://youtu.be/aLx0C8H6qt8 Coming from Second Harvest Food Bank, San Jose (camera…

• less than a min read
thanksgiving , alto , xerox , PARC

Breakfast Bytes

IEDM Preview 2017

Every December is IEDM, the IEEE International Electron Devices Meeting (IEDM). This…

• 5 min read
Intel , IBM , 3D NAND , copper , FinFET , GlobalFoundries , MRAM , IEDM , electron devices

Whiteboard Wednesdays

Whiteboard Wednesdays - Simplifying Fault Injection Simulations for Functional Safety…

In this week's Whiteboard Wednesday, YJ Patil answers the "What", "Why", and "How…

• less than a min read
Automotive , Whiteboard Wednesdays , functional safety

Breakfast Bytes

Jasper User Group 2017

This year's Jasper User Group (JUG) took place on 7th November. It was the 10th JUG…

• 6 min read
Jasper User Group , aruba , JUG , formal , ARM , JasperGold

Breakfast Bytes

How's Technology in Israel?

Last week was the last CDNLive of 2017 (cats have nine lives, Cadence had nine CDNlives…

• 10 min read
CDNLive , mellanox , machine learning , Lip-Bu Tan , Anirudh Devgan , eyal wladman , Israel

Learning and Support

Using Search Filters to Improve Search Results on support.cadence.com

While using any search engine, you might often feel there is too much information…

• 1 min read
COS , Search Filters , Search , Cadence Online Support , Cadence Support Portal , Cadence support

Analog/Custom Design

Virtuosity: All New XStream In - The Translation Expressway

A layout design has to go through several iterations and multiple data exchanges…

• 6 min read
xstream in , design data translator , xstream in import , eda import

Breakfast Bytes

Arm Security Manifesto...and Krack

The Internet of Things (IoT) could be a big number...20 billion things... 50 billion…

• 7 min read
security , ARM Techcon , Simon Segars , security manifesto , reaper , wi-fi , mira , ARM , krack

Digital Design

How to Measure and Improve Design Regularity for Better Yield

The following post is an excerpt of “Methodology for Analyzing and Quantifying Design…

• 1 min read
pattern analysis , machine learning , analytics , yield , silicon signoff , design for manufacturing , DFM

Breakfast Bytes

Social Engineering

The biggest weakness in security are the people. It is almost never the encryption…

• 6 min read
security , spearphishing , phishing , social engineering , ARM , ddos , Techcon

System, PCB, & Package Design 

How to Be Sure Your PCB Design Is Protected from ESD Events

One way to determine if your design can withstand an electro-static discharge (ESD…

• 4 min read
Time domain , Speed2000 , FDTD , Sigrity , ESD

Verification

Adding Annotations in Your e Code

If you have had a chance to work with languages like Java or C#, you might have come…

• 6 min read
Specman , e , e language , specman elite , annotations

The India Circuit

The Exciting New Product Launched at CDNLive India 2017

One of the highlights at CDNLive India 2017 that was held in September was the launch…

• 3 min read
memory characterization , CDNLive India , cadence , Vinod Kariat , Cadence Legato , Invecas
CDNS - Fix Layout Hompage