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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Analog/Custom Design

Virtuosity: What's New in analogLib

It's been a while since analogLib was updated, so we decided to pay some attention…

• 4 min read
Analog Design Environment , ADE Explorer , Analog Simulation , analog , ADE , Virtuoso , Analog Design Environment , Schematic Editor , Virtuosity , Custom IC Design , Schematic , ADE Assembler

Breakfast Bytes

RISC-V 6th Workshop 上海

The 6th RISC-V workshop was held in early May. It was the first one in Asia, at Shanghai…

• 11 min read
computer architecture , risc-v , risc-v foundation , dave patterson

Breakfast Bytes

What's For Breakfast? Video Preview May 15th to 19th 2017

https://youtu.be/WTQhUyl2BBE Coming from Jing'an Park, Shanghai, China (camera…

• less than a min read
Automotive , dreamchip , CDNLive , CDNLive Munich , Tensilica , software development

Breakfast Bytes

Are General-Purpose Microprocessors Over?

There is apparently a rule of thumb among journalists that when the headline of an…

• 8 min read
Intel , risc-v , processor , MIPS , Tensilica , RISC , ARM , microprocessor , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - CNN Challenges: Compute Requirement

In this week's Whiteboard Wednesdays video, Megha Daga takes a deep dive into compute…

• less than a min read
Whiteboard Wednesdays , convolutional neural networks

Breakfast Bytes

Soft Error Rates in Satellites and Cars

Space turns out to be an interesting area for semiconductors, especially looking…

• 8 min read
Automotive , st microoelectronics , ser , soft error rate , cubesat , see , single event effect , seu , space , Breakfast Bytes , satellite

Breakfast Bytes

NASA: "Never Have Another Accident Due to Our Organizational Flaws"

The keynote at the IRPS reliability conference I attended was by Nancy Currie-Gregg…

• 7 min read
space shuttle , NASA , Breakfast Bytes , reliability

Breakfast Bytes

TSMC @ N7 with Cadence

One presentation at the recent CDNLive Silicon Valley was about using Cadence tools…

• 4 min read
Genus , Tempus , TSMC , n7 , Innovus , Quantus , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: How Can I Plot or Evaluate with the New Expression Builder…

Indeed, the new Expression Builder has made expression creation much easier, but…

• 3 min read
Analog Design Environment , evaluateADE Explorer , Analog Simulation , plot , expressions , analog , Mixed-Signal , Expression Builder , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design , calculator

Breakfast Bytes

UVM Is Now IEEE 1800.2 and There's a Ten-Year Story to That

UVM, the Universal Verification Methodology, just became IEEE 1800.2-2017. I wondered…

• 6 min read
SystemVerilog , Superlog , ieee 1800.2 , uvm , Accellera , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview May 8th to 12th 2017

https://youtu.be/sIFo4JKjVxw Coming from NASA Ames Research Center, Sunnyvale…

• less than a min read
space shuttle , risc-v , NXP , ser , 22fdx , soft error rate , 12fdx , Samsung , single event upset , Tensilica , single event effect , ST Microelectronics , GlobalFoundries , ARM , microprocessor , NASA , reliability , FD-SOI

Breakfast Bytes

Bayern München Will Not Be at CDNLive Munich: Here's What They Will Miss

Yes, it's true. After attending CDNLive EMEA for the last couple of years, Bayern…

• 3 min read
Automotive , NXP , Munich , CDNLive , CDNLive EMEA , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays – Introduction to Cadence Tensilica Vision C5 DSP

In this week's Whiteboard Wednesdays video, Pulin Desai describes the main features…

• less than a min read
Whiteboard Wednesdays , Vision DSP , convolutional neural networks , CNN

Breakfast Bytes

Test Flying Pegasus

Scott Barric of MicroSemi is one of the people who have been using the pre-release…

• 5 min read
Physical verification , pegasus , DRC , cloud , microsemi , design rule check , PVS , Breakfast Bytes , cloud computing

Digital Design

Designing for Low Power… Begin at the Beginning

So you have your RTL written, and it’s time to optimize to reduce power. If that…

• 3 min read
Low Power , high level synthesis , power , HLS

Analog/Custom Design

Virtuosity: The Reboot

It’s been quite a while since I wrote about “Things I Learned by Browsing Cadence…

• 2 min read
Analog Design Environment , ADE GXL , ADE Explorer , Rapid Adoption Kit , Analog Simulation , ADE XL , ADE , ADE-GXL , Analog Design Environment , ADE-XL , Virtuosity , Custom IC Design , ADE Assembler

Breakfast Bytes

Vision C5 DSP for Standalone Neural Network Processing

I pointed out recently that although La La Land is a romance, the movie opens with…

• 6 min read
DSP , Vision C5 , embedded vision , Embedded Vision Alliance , Tensilica , semiconductor IP , embedded vision conference , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 1

In this week's Whiteboard Wednesdays video, Tom Hackett traces the evolution of the…

• less than a min read
Whiteboard Wednesdays , ccix

Breakfast Bytes

Growth Comes from Solving New Problems—ESD Alliance CEO Panel

First, some sad news. Bob Gardner, for many years the executive director of the ESD…

• 12 min read
cadence , EDAC , arm holdings , ARM , synopsys , Breakfast Bytes , esd alliance , Mentor
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