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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

Cadence Online Support — Empowering Learning! New Features from July 2016

Lots of documents are posted on Cadence Online Support on regular basis. Let us take…

• 2 min read
cadence online , "PCB design" , application note , Allegro

Breakfast Bytes

CDNLive Boston Overview

CDNLive Boston took place last week. It is really CDNLive East Coast, and there were…

• 6 min read
CDNLive , Power Integrity , cdnlive boston , Signal Integrity , Breakfast Bytes

Breakfast Bytes

RISC-V Gathering Momentum

I've been writing quite a bit about RISC-V (pronounced "risk five") since I think…

• 4 min read
krste asonovic , risc-v , codasip , NVIDIA , google , andes , cortus , Breakfast Bytes , sifive , hp enterprise

Breakfast Bytes

Happy Birthday, HP 12c—35 Years and Counting

Last year was the 50th anniversary of Moore's Law. One consequence of Moore's Law…

• 3 min read
hewlett-packard , hp 12c , CMOS , hp12c , calculator , Breakfast Bytes

Verification

DisplayPort 8K in Olympics 2020

If you’re anything like me, you’ve spent the last couple of weeks glued to the TV…

• 3 min read
Verification IP , VIP , DisplayPort , Design and Verification IP , Olympics

Breakfast Bytes

What’s for Breakfast? Preview September 6th to 9th (video)

https://youtu.be/lD8VFUNds7o Monday: Labor Day. Tuesday: CDNLive Boston. I…

• less than a min read
risc-v , acquila , CDNLive , MIPI , Power Integrity , open cellular , cdnlive boston , mipi devcon , Facebook , Signal Integrity , sifive

Breakfast Bytes

MIPI SoundWire

The MIPI Alliance exists to standardize widely used interfaces in mobile, such as…

• 3 min read
USB Type-C , MIPI SoundWire , MIPI , lightning , Soundwire , RealTek

Analog/Custom Design

Virtuoso Video Diary: Introducing WSP Manager

Are you an advanced node layout or CAD engineer trying to find a methodology for…

• 2 min read
Routing , WSP , Rapid Adoption Kit , Advanced Node , Virtuoso Video Diary , Custom IC Design , Virtuoso Layout Suite

Whiteboard Wednesdays

Whiteboard Wednesdays - Application-Optimized DDR PHYs

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty takes a closer look…

• less than a min read
Whiteboard Wednesdays , memory subsystems , memory IP , DDR IP , DDR PHY

System, PCB, & Package Design 

Sneak Peek: Discussion Topics for Signal and Power Integrity Expert Panel at CDNLive…

Who? Istvan Novak - senior principal engineer at Oracle Kevin Roselle -…

• 2 min read
Power Integrity , cdnlive boston , Signal Integrity , PCB design

Breakfast Bytes

Aging and Self-Heating in FinFETs

At CDNLive in India, Cadence's Hany Elhak discussed aging and self-heating, and how…

• 3 min read
failure , CDNLive India , Spectre , self-heating , aging , FinFET

SoC and IP

HoloLens Is at the Tip of the Tensilica Iceberg, With Processors That Scale to Any…

Microsoft provided details of their HoloLens HPU at HotChips this week, revealing…

• less than a min read
IP , controller , Tensilica , augmented reality

Breakfast Bytes

Piloted Driving: Audi's View

I hope it isn't a surprise to anyone reading this blog that the share of a vehicle…

• 3 min read
Automotive , Audi , automotive electronics , imec , itf brussels , itf

Breakfast Bytes

A Raven Has Landed: RISC-V and Chisel

In Game of Thrones, ravens are George RR Martin's way of getting information around…

• 4 min read
risc-v , riscv , chisel , raven , UC Berkeley , Breakfast Bytes

Academic Network

ISVLSI 2016: Advanced-Node Custom Layout Symposium Keynote

I had an exciting week in July here in Pittsburgh, PA with the IEEE Computer Society…

• 2 min read
ISVLSI , VLSI , Cadence Academic Network , academia , Virtuoso , advanced node layout

Breakfast Bytes

Provisioning Devices Securely

Asaf Ashkenazi of Cryptography Research (now part of Rambus) talked about provisioning…

• 3 min read
provisioning , security , cryptography research , IoT , wearables , linley mobile , Internet of Things , Breakfast Bytes

Breakfast Bytes

Who Put the Silicon in Silicon Valley?

I think the person who has the strongest claim to putting the silicon in Silicon…

• 5 min read
marc andreessen , William Shockley , Silicon Valley , Breakfast Bytes

Computational Fluid Dynamics

Ford: Multidisciplinary Design Optimization of a Turbocharger Compressor

Ford chooses Fidelity Optimization to increase the performance of turbocharger compressors…

• 4 min read
CFD , Automotive , automotive engineering , turbomachinery , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , CFD Applications , Turbo

Breakfast Bytes

What’s for Breakfast? Preview August 29th to September 2nd (video)

https://youtu.be/X-hVSQfbtFE

• less than a min read
self-heading , Apple , risc-v , Audi , CDNLive , autonomous driving , MIPI , isa , cdnlive boston , Soundwire , aging , FinFET , ADAS , piloted driving , Krste Asanović , instruction set architecture
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