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Featured

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
Corporate 2 Jun 2026 • 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
Corporate 31 May 2026 • 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
Corporate 21 May 2026 • 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
Corporate 20 May 2026 • 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

  • All 6375
  • Corporate News 259
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  • Academic Network 169
  • Analog/Custom Design 801
  • Artificial Intelligence 26
  • Cloud 23
  • Computational Fluid Dynamics 372
  • Data Center 57
  • Digital Design 458
  • Learning and Support 62
  • RF Engineering 116
  • SoC and IP 435
  • System, PCB, & Package Design  1015
  • Verification 1321
  • Cadence Japan 17
  • Physical Systems Simulation 5

  • CFD(数値流体力学) 45
  • 中文技术专区 9
  • カスタムIC/ミックスシグナル 199
  • PCB、IC封装:设计与仿真分析 136
  • PCB解析/ICパッケージ解析 44
  • PCB設計/ICパッケージ設計 61
  • RF /マイクロ波設計 45
  • Spotlight Taiwan 64
  • The India Circuit 93
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

Verification

A Brief Introduction to Xcelium

Welcome to the XTeam blog! We are a team of bloggers dedicated to showcasing the…

XTeam 9 Jun 2017 • less than a min read
Low Power , digital mixed signal , Functional Verification , Multi-Core , xcelium , parallel simulation

Breakfast Bytes

Pre-Silicon Software Development with Protium and Palladium Platforms

We've already had CDNLive EMEA, but here is a look at a presentation from CDNLive…

Paul McLellan 9 Jun 2017 • 5 min read
debug , android , Protium , Palladium , embedded software , software development , linux , Breakfast Bytes

Breakfast Bytes

Schematic-Driven Simulation and Layout of Complex Photonic ICs

Photonics is transmitting data through fiber optic cables. As such, photonics is…

Paul McLellan 8 Jun 2017 • 5 min read
PhoeniX Software , Lumerical , silicon photonics , Virtuoso , photonics , Breakfast Bytes

Breakfast Bytes

Cadence at DAC

Yes, it's nearly here, the 54th Design Automation Conference in Austin, Texas (and…

Paul McLellan 7 Jun 2017 • 7 min read
DAC , Joe Costello , expert bar , Cadence Theater , 54dac , Denali Party , Accellera , cooley troublemaker panel , #54dac , pss , cadence lunches , Breakfast Bytes , portable stimulus standard

Whiteboard Wednesdays

Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 2

In this week's Whiteboard Wednesdays video, Tom Hackett completes the story of the…

References4U 6 Jun 2017 • less than a min read
Whiteboard Wednesdays , ccix

Breakfast Bytes

What's For Breakfast? Video Preview June 12th to June 16th 2017

https://youtu.be/oikFfm15nw8 Coming from Samsung@First (camera Sean) Monday…

Paul McLellan 6 Jun 2017 • less than a min read
kqed forum , embedded vision , Samsung , computer history museum , samsung foundry forum , EUV , FD-SOI

Digital Design

2017 Annual HLS Survey Results

As many of you know, Cadence (more correctly, “I”) recently performed an industry…

dpursley 6 Jun 2017 • 4 min read
High-Level Synthesis , survey , Stratus , HLS

Breakfast Bytes

Rowen: How to Start an Embedded Vision Company

The last presentation that I'll cover in its own post from this year's Embedded Vision…

Paul McLellan 6 Jun 2017 • 6 min read
Chris Rowen , Embedded Vision Summit , embedded vision , Tensilica , Breakfast Bytes

Breakfast Bytes

Bier Goggles: 1000X in 3 Years

Jeff Bier heads up the Embedded Vision Alliance (and, in his day job, he heads up…

Paul McLellan 5 Jun 2017 • 4 min read
Embedded Vision Summit , deep neural networks , Embedded Vision Alliance , BDTI , dnn , neural networks , Breakfast Bytes

Breakfast Bytes

Deep Understanding, Not Just Deep Vision

The keynote on the second day of the Embedded Vision Summit was by Jitendra Malik…

Paul McLellan 2 Jun 2017 • 10 min read
convolutional neural nets , dnn , neural networks , CNN , neural nets , Breakfast Bytes

Breakfast Bytes

Lifting the Veil on Hololens

The opening keynote at the Embedded Vision Summit in Santa Clara was by Marc Pollefeys…

Paul McLellan 1 Jun 2017 • 7 min read
hololens , microsoft , Embedded Vision Summit , Tensilica , vision , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview June 5th to June 9th 2017

https://youtu.be/C7nOhT8ey7g Coming from Cadence Cafeteria (camera Sean) …

Paul McLellan 31 May 2017 • less than a min read
DAC , 54dac , palldium , Protium , embedded vision , Embedded Vision Alliance , silicon photonics , #54dac , Design Automation Conference

Breakfast Bytes

Embedded Vision Summit: "It's a Visual World"

"It's a visual world," Tim Ramsdale of ARM said at one point in the recent Embedded…

Paul McLellan 31 May 2017 • 12 min read
embedded vision , deep neural networks , Tensilica , convolutional neural networks , neural nets , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Vision C5 DSP: A Solution to Current Challenges and Trends…

In this week's Whiteboard Wednesdays video, Megha Daga talks about how Cadence did…

References4U 30 May 2017 • less than a min read
Whiteboard Wednesdays , convolutional neural networks

Breakfast Bytes

Virtuoso System Design Platform

Cadence was already talking about chip-package-board back in 2000 when I was putting…

Paul McLellan 30 May 2017 • 3 min read
package , board , 2.5D packagin , Virtuoso , 3D packaging , interposer , Sigrity , Custom IC , Breakfast Bytes , Allegro

Academic Network

10 years Academic Network at CDNLive EMEA, a Reason To Celebrate!

From 15-17 May CDNLive EMEA opened again its doors for around 700 attendees from…

Anton Klotz 26 May 2017 • 5 min read
Cadence Academic Network , CDNLive , BarCamp , Functional Verification , academic workshop , academia , MEMS Design Contest , CDNLive EMEA , Cadence Design Contest , university program

Analog/Custom Design

Virtuoso Video Diary - Filtering Your Way Through Corners

Have you ever looked at the Corners Setup form and wished you had some way of finding…

Arja H 26 May 2017 • 4 min read
Analog Design Environment , ADE Explorer , Explorer , Analog Simulation , ADE , Virtuoso , Analog Design Environment , Virtuosity , Virtuoso Video Diary , Custom IC Design , ADE Assembler

Breakfast Bytes

HOT Party Remembers Gary Smith...and the Denali Party

Every year at DAC, Heart of Technology (HOT) organizes a charity event. This year…

Paul McLellan 26 May 2017 • 2 min read
DAC , HOT , Heart of Technology , Gary Smith , sjsu , Design Automation Conference , Breakfast Bytes

System, PCB, & Package Design 

Epic Western Movies and PCB Design. Seriously.

I love that recently Westerns movies are making a comeback. Something about the romanticism…

Darintb 25 May 2017 • 2 min read
PCB , PCB Layout and routing , Routing , PCB Co-Design , Symphony , Team design , PCB Editor , PCB design , Allegro PCB Editor , Allegro
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