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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Breakfast Bytes

DAC Tuesday 2017: Siemens, SiP, Simon & Lucio, Neural Nets, Nenni, Denali, and M…

Yesterday was Tuesday at DAC here in Austin. For reports on the last couple of days…

• 15 min read
Simon Segars , SiP , Semiwiki , silicon in package , Denali Party , Lucio Lanza , Siemens , neural networks , 7nm , ARM , Breakfast Bytes , Mentor

Breakfast Bytes

DAC Monday 2017: Joe, Lip-Bu, China, Under 40s, Smurfs, and More

It's Monday, the first real day of DAC after the kickoff on Sunday evening. See Guide…

• 12 min read
Joe Costello , 54dac , Lip-Bu Tan , chipestimatetv , #54dac , Breakfast Bytes

Verification

Cadence @ DAC: What to Expect and What to See

Cadence returns to DAC 2017 this year, showcasing our full verification suite. Here…

• 3 min read
DAC , methodology , EDA , Formal verification , verification

Breakfast Bytes

Sean and Paul DAC Walkthrough

Sean O'Kane and I wandered around the show floor during setup on Sunday and looked…

• less than a min read
54dac , chipestimatetv , Design Automation Conference

Verification

New VIP for ARM AMBA 5 CHI Issue B

In coordination with the announcement of the new ARM® AMBA® 5 Coherent Hub Interface…

• 3 min read
Verification IP , VIP , AMBA , ARM , CHI VIP

Breakfast Bytes

Guide to Austin for Newbies, and DAC Sunday Kickoff

This is my first post from DAC. I will be posting each day about the most interesting…

• 10 min read
54dac , Austin , Gary Smith EDA , iron works barbecue , franklin barbecue , #54dac , barbecue , Breakfast Bytes

Breakfast Bytes

Visual Baggage

If you have been watching my "What's for Breakfast?" weekly video previews, then…

• 7 min read
embedded vision , convolutional neural nets , autonomous vehicles , neural nets , Breakfast Bytes

Verification

See Perspec Running Accellera Portable Stimulus Examples Here and Now!

Accellera has announced the release of an Early Adopter specification of the Portable…

• less than a min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Verification

Accellera Has Done It Again! Portable Stimulus Standard Available For Review

In a press release this morning, Accellera announced availability of an Early Adopter…

• 2 min read
CDNS , Perspec , Accellera , pss , portable stimulus

Analog/Custom Design

Virtuoso Video Diary: What is Virtuoso System Design Platform?

“Any sufficiently advanced technology is indistinguishable from magic.” ― Arthur…

• 4 min read
ADE Explorer , ADE , Virtuoso Layout Suite L , Schematic Editor , Virtuoso Video Diary , Sigrity , Custom IC Design , Allegro

Academic Network

Cadence Research Workshop in Duke Kunshan University

Cadence Academic Network (CAN) hosted a Cadence Research Workshop in Duke Kunshan…

• less than a min read
Cadence Academic Network , academic workshop , academia

Breakfast Bytes

Breakfast Bytes Brought to You By... KQED?

If you live in the Bay Area, you have almost certainly heard KQED's Forum program…

• 6 min read
kqed , wired , mixed reality , fake reality , pbs , virtual reality , fake news , augmented reality

Analog/Custom Design

Virtuosity: New Modgen and Row-Based Placement Rapid Adoption Kits

Cadence Rapid Adoption Kits (RAKs) are designed to help users quickly adopt new technologies…

• 3 min read
Row Region , EAD , Row Template , Modgen On Canvas , MODGEN , Rapid Adoption Kit , Virtuoso Placer , RAK , VLS GXL , Layout , Virtuosity , Custom IC Design , modgens , RAKs , Virtuoso Layout Suite , Row-Based Placement

Breakfast Bytes

Samsung Foundry Forum: Beyond FinFET and FD-SOI

This is the third post on the second Samsung Foundry Day held recently. The first…

• 4 min read
IBM , envm , emram , horizontal nanosheet , rf-soi , GlobalFoundries , EUV , Breakfast Bytes , FD-SOI

Whiteboard Wednesdays

Whiteboard Wednesdays - 3 Market Forces Driving Commercial IP Adoption

In this week's Whiteboard Wednesdays video, Tom Hackett explains the 3 forces driving…

• less than a min read
Design IP , Whiteboard Wednesdays , IP , interfaces

Breakfast Bytes

What's For Breakfast? Video Preview June 19th to June 23rd 2017

https://youtu.be/QtKiDx9yXAY Coming from the Staten Island Ferry NY (camera…

• less than a min read
DAC , 54dac , Design Automation Conference

Breakfast Bytes

Samsung Foundry Forum: EUV

This is the second post on the second Samsung Foundry Day held recently. The first…

• 5 min read
Samsung , samsung foundry , EUV , Breakfast Bytes

Analog/Custom Design

Virtuosity: I've Learned to Customize RTT Simulations...Bingo!

The Real-Time Tuning (RTT) assistant is one of the most powerful features of ADE…

• 4 min read
Analog Design Environment , custom/analog , ADE Explorer , Explorer , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , Virtuosity , Custom IC Design

Breakfast Bytes

Samsung Foundry Forum: Roadmaps

I attended the second Samsung Foundry Forum. As seems to be traditional for foundries…

• 4 min read
8nm , Samsung , samsung foundry , Qualcomm , 5nm , 7nm , 10nm , EUV , Breakfast Bytes
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