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The India Circuit

CDNLive India Keynote: Qualcomm On 5G And More

CDNLive India concluded last Friday and what an event it was! With 87 paper presentations…

Madhavi Rao 13 Sep 2017 • 4 min read

5G , artificial intelligence , CDNLive India , CDNLive , IoT , machine learning , Qualcomm , mobile , 7nm

Breakfast Bytes

New Cadence Support of TSMC 7nm, 7nm+, and 12FFC

A quick guide to TSMC processes. There is a 10nm process but very little development…

Paul McLellan 13 Sep 2017 • 4 min read

OIP , 7nm+ , 12FFC , TSMC , DDR , 7nm , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Benchmarking Deep Learning Platforms: The Results

In this week's Whiteboard Wednesdays video, Mengjun Leng follows up on last week…

References4U 12 Sep 2017 • less than a min read

Whiteboard Wednesdays , deep learning

SoC and IP

Cadence IP Is Great for Automotive

If you’re designing chips for in-vehicle infotainment, in-cabin electronics, vision…

PaulaJones 12 Sep 2017 • less than a min read

USB 3.0 , Design IP , DDR4 , LPDDR4 , PCI Express 3.0 , LPDDR , IP blocks , PCIe Gen4 , MIPI , DisplayPort , Automotive Ethernet , USB , memory IP , Ethernet , PCIe , 16nm , PCIe Gen3 , imaging , Ethernet PHYs , PCI

Verification

How to Get to a Trillion Devices in the Internet of Things in 2035

Next month at Arm TechCon, one of the key discussion topics with be the internet…

fschirrmeister 12 Sep 2017 • 4 min read

prototyping , cadence , palladium z1 , IoT , Socrates , Emulation , Internet of Things , ARM , protium s1 , verification

Analog/Custom Design

Virtuosity: Driving Along a Longer Route May Take You Home Sooner!

On my way back home every day, I need to make a decision — should I drive less, or…

Rishu Misri Jaggi 12 Sep 2017 • 4 min read

library manager , Virtuoso , Virtuosity , physConfig , CPH , copy library , Custom IC

Breakfast Bytes

Automotive IP Family for TSMC 16FFC

At the semiconductor level, automotive poses huge challenges due to an experience…

Paul McLellan 12 Sep 2017 • 3 min read

OIP , tsmc 9000A , TSMC , renasas , Ethernet , PCIe , semiconductor IP , DDR , Breakfast Bytes

Digital Design

Why Pegasus Is the Biggest Breakthrough in SoC Physical Verification in 20 Years…

These days, DRC rule deck availability for the market tools is not a major issue…

Manoj Chacko 11 Sep 2017 • 3 min read

Physical verification , massively scalable , pegasus , DRC , Cloud ready

Breakfast Bytes

Xilinx/Arm/Cadence/TSMC Announce World's First 7nm CCIX Silicon Demonstrator; and…

"It takes a village to raise a child," as the African proverb says. It seems to take…

Paul McLellan 11 Sep 2017 • 3 min read

ARM Techcon , cadence , ccix , TSMC , accelerator , xilinx , 7nm , Breakfast Bytes , FPGA

Breakfast Bytes

CDNLive Boston Keynotes

There were three keynotes to kick off CDNLive Boston. Tom Beckley gave the Cadence…

Paul McLellan 8 Sep 2017 • 8 min read

Automotive , Tom Beckley , Protium , Palladium , silicon photonics , ADAS , Medtronic , Breakfast Bytes

Breakfast Bytes

Neural Engineering System Design

At HOTCHIPS 2017, we had a special break so we could watch the eclipse. Of course…

Paul McLellan 7 Sep 2017 • 4 min read

brain encoding , neuron , hotchips , Breakfast Bytes , cortical modem

Analog/Custom Design

Virtuosity: Saving, Loading and Sharing ADE Annotation Settings

The whole ADE annotation flow was overhauled way back in IC6.1.6 but at that time…

Arja H 7 Sep 2017 • 4 min read

ADE Explorer , Annotation Settings , ADE Annotations , ADE , Analog Design Environment , Schematic Editor , Virtuosity , Schematic , ADE Assembler , annotation setup

Breakfast Bytes

What's For Breakfast? Video Preview September 11th to 15th 2017

https://youtu.be/ljGLKZ0gz8c Coming from Singapore Botanic Garden (camera Page…

Paul McLellan 6 Sep 2017 • less than a min read

OIP , ccix , TSMC

Breakfast Bytes

Quantus FS Field Solver for the FinFET Era

For any parasitic extraction tool, there is always a tradeoff between performance…

Paul McLellan 6 Sep 2017 • 4 min read

Extraction , netlist , field solver , quantus fs , Breakfast Bytes , foundry

Verification

How To Create L3 Cache Command Overflow Stress Test in Less Than 2 Days

One category of difficult SoC tests to create are stress tests, to validate the limits…

Steve Brown 5 Sep 2017 • 4 min read

SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Whiteboard Wednesdays

Whiteboard Wednesdays - Benchmarking Deep Learning Platforms

In this week's Whiteboard Wednesdays episode, Mengjun Leng investigates different…

References4U 5 Sep 2017 • less than a min read

Whiteboard Wednesdays , deep learning

Breakfast Bytes

Naveed Sherwani Takes the Reins at SiFive

A couple of weeks ago, I talked to Naveed Sherwani, the new CEO of SiFive. For more…

Paul McLellan 5 Sep 2017 • 5 min read

ASIC , risc-v , naveed sherwani , Breakfast Bytes , sifive

Analog/Custom Design

Virtuoso Video Diary: What Are Parametric Sets?

Over the past few IC6.1.7 and ICADV12.3 ISR releases, a lot of new and useful features…

Ashu V 4 Sep 2017 • 4 min read

Analog Design Environment , ADE Explorer , Explorer , analog , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , Virtuoso Video Diary , Circuit Design , mixed signal , Custom IC Design , Assembler , custom design technology , ADE Assembler , Cusstom IC Design

Breakfast Bytes

Four Early Computers, 3 and 4

This is a continuation of Four Early Computers: 1 and 2 . The story opens as our…

Paul McLellan 1 Sep 2017 • 7 min read

ibm 1130 , ibm 370 , computer history museum , icl , ibm 360 , vax 11/780 , Breakfast Bytes , data general nova

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