Cadence Community

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Latest blogs

Academic Network

EDA Summer Camp—Cadence Taiwan Hosts Top University Students

To help more students majoring in Electronics Engineering increase their understanding…

Tracy Zhu 24 Sep 2017 • 1 min read

Cadence Academic Network , academic workshop , academia , EDA

Verification

Making it Easier to Apply Palladium Z1 to SoC Performance Analysis

Recently, Renesas combined the Cadence® Interconnect Workbench, the Cadence vManager…

XTeam 23 Sep 2017 • 1 min read

Interconnect Workbench , customer feedback , success story , Palladium , Renesas

Analog/Custom Design

The Art of Analog Design: Part 3, Monte Carlo Sampling

In Part 2, we looked at Monte Carlo sampling methods. In Part 3, we will consider…

Art3 22 Sep 2017 • 4 min read

Analog Design Environment , APS , ADE Explorer , Analog Simulation , analog , ADE , Monte Carlo , Analog Design Environment , ViVA , ADE Assembler , Cusstom IC Design

Breakfast Bytes

What's For Breakfast? Video Preview September 25th to 29th 2017

https://youtu.be/Uubpn09k83U Coming from Testarossa Winery, Los Gatos (camera…

Paul McLellan 22 Sep 2017 • less than a min read

semi , business models , EDPS , sjsu , Jim Hogan , neural nets , smc

Analog/Custom Design

Virtuosity: Sweeping Multiple DSPF Views in ADE

Wouldn't it be great if you could have a view for your DSPF files and sweep them…

Arja H 22 Sep 2017 • 3 min read

Analog Design Environment , ViVa-XL , custom/analog , ADE Explorer , Analog Simulation , DSPF , ADE , Block-level simulation , Virtuoso Analog Design Environment , Analog Design Environment , Schematic Editor , ViVA , Virtuosity , Circuit Design , Custom IC Design , Schematic , ADE Assembler

Breakfast Bytes

Show Me the Money

I have put out some posts about generic business models and startups. However, if…

Paul McLellan 22 Sep 2017 • 7 min read

investors , EDA , startups , Breakfast Bytes

Breakfast Bytes

Coincidence and Another Record

Record 1 I recently reached a sort of record that I detailed in my post The 500th…

Paul McLellan 21 Sep 2017 • 6 min read

SIA , hock tan , gsa , Breakfast Bytes

The India Circuit

CDNLive India 2017: ThinCi on AI, Machine Learning and Deep Learning

Last week’s blog was about Venu Puvvada’s keynote at CDNLive India. Today’s blog…

Madhavi Rao 20 Sep 2017 • 4 min read

artificial intelligence , CDNLive India , deep learning , CDNLive , ThinCi , machine learning

Breakfast Bytes

India, Singapore, Hong Kong

What do India, Singapore, and Hong Kong have in common? Well, I visited them all…

Paul McLellan 20 Sep 2017 • 8 min read

CDNLive , lee kuan yew , hong kong , sir john cowperthwaite , bangalore , Breakfast Bytes , India , Singapore

Whiteboard Wednesdays

Whiteboard Wednesdays - Implementation Challenges of Embedded Automatic Speech Recognition…

In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, talks…

References4U 19 Sep 2017 • less than a min read

Whiteboard Wednesdays , Automatic Speech Recognition

SoC and IP

USB 3.2—The USB Type-C Connector Finally Met its Match

It’s only a week before the first event of USB Developer Days , a series of meetings…

Jacek Duda 19 Sep 2017 • 1 min read

USB 3.0 , USB Type-C , DisplayPort , USB , USB 3.2 , power delivery , USB 3.1

Breakfast Bytes

CDNLive India 2017 Trip Report

I went to Bangalore to CDNLive India. It has a different structure from the other…

Paul McLellan 19 Sep 2017 • 6 min read

ml , CDNLive India , dl , CDNLive , machinelearningdeeplearning , AI , Breakfast Bytes

Analog/Custom Design

Virtuosity: Sweeping Multiple Config Views

Before IC6.1.7 ISR10, you could sweep multiple views in ADE for only one block in…

Arja H 18 Sep 2017 • 2 min read

Analog Design Environment , ADE Explorer , Explorer , Analog Simulation , ADE , Virtuoso Analog Design Environment , Analog Design Environment , Schematic Editor , Virtuosity , Circuit Design , Custom IC Design , Schematic , ADE Assembler