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Featured

Corporate News

DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

Every year, Design Automation Conference (DAC) brings big announcements, packed demos…

Veena Parthan
Veena Parthan 7 Aug 2026 • 5 min read
Jasper Formal Verification Platform , featured , agentic ai , DAC 2026 , AI for design

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
Corporate 31 Jul 2026 • 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
Corporate 27 Jul 2026 • 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
Corporate 26 Jul 2026 • 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA
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Blog - Post List
Latest blogs

Breakfast Bytes

The SDE Circle of Life Today

This is the second part of a two-part post about the SDE Circle of Life. The first…

Paul McLellan 27 Mar 2017 • 5 min read
Automotive , SDE , mobile , system design enablement , iPhone

Breakfast Bytes

The SDE Circle of Life

There seems to be a big picture phenomenon that I like to call the System Design…

Paul McLellan 24 Mar 2017 • 5 min read
Automotive , SDE , mobile , system design enablement

Verification

A Seamless Path to the Portable Stimulus Standard

In our last blog post , we reviewed some of the activities at the recent Design and…

tomacadence 23 Mar 2017 • 3 min read
uvm , prototyping , pswg , Acceleration , Functional Verification , Perspec , System Design and Verification , Palladium , SoC , Emulation , Simulation acceleration , DVcon , Accellera , metric-driven verification , Hardware/software co-verification , portable stimulus , simulation , verification

Breakfast Bytes

Léman Micro Devices: Blood Pressure on Your Smartphone

One of the most interesting things I saw at MWC was a meeting I had with Mark-Eric…

Paul McLellan 23 Mar 2017 • 6 min read
Léman Micro Devices , medical electronics , mobile , cadence hosted design environment , blood pressure , Smartphone

Breakfast Bytes

TSMC Technology Symposium 28...22...16...12...7...

This is the second of two posts about last week's TSMC Technology Symposium. The…

Paul McLellan 22 Mar 2017 • 7 min read
OIP , n5 , 12FFC , TSMC , TSMC Technology Symposium , n7+ , n7

Whiteboard Wednesdays

Whiteboard Wednesdays - Introduction to Convolutional Neural Networks (CNN)

In this week's Whiteboard Wednesdays video, the first in a two-part series, Megha…

References4U 21 Mar 2017 • less than a min read
Automotive , deep learning , vision , convolutional neural networks , mobile , ADAS , CNN

Breakfast Bytes

What's For Breakfast? Video Preview March 27th to 31st 2017

https://youtu.be/-_33atq9vRY Coming from National Automobile Museum, Reno,…

Paul McLellan 21 Mar 2017 • less than a min read
ESDA , circle of life , lanza techventures , Lucio Lanza , system design enablement , SDA , esd alliance , virtual dummy metal fill

Breakfast Bytes

TSMC Technology Roadmaps

TSMC had their annual Technology Symposium last week. As always, my post comes with…

Paul McLellan 21 Mar 2017 • 6 min read
Automotive , n5 , IoT , TSMC , HPC , n7 , mobile , n10

Academic Network

The Worldwide MEMS Design Contest Officially Starts

Cadence, X-FAB, Coventor and Reutlingen University have Selected 10 Design Teams…

ChristinaK 20 Mar 2017 • 2 min read
Cadence Academic Network , X-FAB , MEMS Design Contest , Reutlingen University , CDNLive EMEA , Mixed-Signal , Coventor

Breakfast Bytes

CDNLive Silicon Valley Preview

Yes, it's that time of year again. Just like a cat has nine lives, Cadence has nine…

Paul McLellan 20 Mar 2017 • 2 min read
microsoft , CDNLive , Santa Clara Convention Center , CDNLive Silicon Valley

Breakfast Bytes

Dracula, Vampire, Assura, PVS: A Brief History

Cadence was created from the merger of SDA and ECAD, as you probably know. SDA had…

Paul McLellan 17 Mar 2017 • 9 min read
Extraction , Dracula , DRC , vampire , design rule check , Assura

Breakfast Bytes

Andy Bechtolsheim Keynote on the Future of Networking

At the recent Linley Cloud Hardware Conference, the keynote was given by Andy Bechtolsheim…

Paul McLellan 16 Mar 2017 • 7 min read
andy bechtolsheim , arista networks , andreas bechtolsheim , linley cloud hardware conference , Linley

Breakfast Bytes

TSMC Announces New 12FFC Process

Today at the TSMC Technology Symposium, Cliff Hou, TSMC's VP of R&D, is set to announce…

Paul McLellan 15 Mar 2017 • 4 min read
Design IP , 12FFC , TSMC , TSMC Technology Symposium , 12nm , InFO , 7nm

Breakfast Bytes

What's For Breakfast? Video Preview March 20th to 24th 2017

https://youtu.be/Qm8epP4YobA Coming from TSMC Technology Symposium, Santa Clara…

Paul McLellan 15 Mar 2017 • less than a min read
Léman Micro Devices , CDNLive , SDE , 12FFC , TSMC , TSMC Technology Symposium , InFO , mobile , blood pressure , system design enablement , 7nm , Smartphone

Analog/Custom Design

Virtuoso Video Diary: Real-Time Tuning—A Lot More Than Just an Assistant!

Have you ever found yourself in situations where you’re not sure which values of…

Ashu V 15 Mar 2017 • 3 min read
Analog Design Environment , ADE Explorer , Analog Simulation , analog , Mixed-Signal , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design

Whiteboard Wednesdays

Whiteboard Wednesdays - Display Stream Compression: Higher Display Resolutions in…

In this week's Whiteboard Wednesdays video, Alex Passi takes a closer look at Display…

References4U 14 Mar 2017 • less than a min read
mobile devices , Whiteboard Wednesdays , MIPI , MIPI protocols

Breakfast Bytes

Cadence at MWC: Does This Headset Make Me Look Silly?

Cadence has attended MWC ever since it acquired Tensilica, and they attended for…

Paul McLellan 14 Mar 2017 • 4 min read

Digital Design

Have DRC Tools Run Out of Steam? – Part 1

In the EDA history of design rule check (DRC), there have been two distinct eras…

Christen 13 Mar 2017 • 3 min read
Physical verification , DRC , design rule check

Breakfast Bytes

ESD Alliance Panel on Energy Policy for the IoT Era

BREAKING NEWS: I just received an email that the panel I wrote about here has been…

Paul McLellan 13 Mar 2017 • 4 min read
california energy commission , energy policy , ESDA , IoT , Internet of Things , san jose city hall , cec , esd alliance
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