Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

Customer Support Recommended—Design and Simulation of Full Bridge DC-DC SMPS Using…

Switched Mode Power Supplies (SMPS) are used extensively in most of the power conversion…

• 4 min read
customer support , AMS simulator , PSPICE , Customer Support Recommended , PCB design , AMS simulation , SPB16.5 , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays - LPDDR4 IP Verification Challenges

In this week's Whiteboard Wednesdays video, YJ Patil discusses the challenges of…

• less than a min read
memory protocols , IP , Mobile SoCs , LPDDR4 , LPDDR4 IP , verifying IP

SoC and IP

Call for Papers for MemCon Now Open

What’s the biggest conference for everything related to memories? If you answered…

• 1 min read
Verification IP , DDR4 , MemCon , LPDDR , VIP , memory IP , Denali , Design IP and Verification IP , memories

SoC and IP

Mobile World Congress: Enabling Systems with Sensor Fusion, DSPs

BARCELONA, Spain—We hear a lot about sensor fusion and the applications that it can…

• 1 min read
DSP , sensor fusion , #MWC15 , cadence , Freespace , Mobile World Congress , Tensilica , Hillcrest Labs

Digital Design

High-Level Synthesis: Why Now?

March 27, 2015 – With a title like “Why Now?”, you might expect this to be a sales…

• 2 min read
High-Level Synthesis , EDA , Forte , Stratus , HLS

Whiteboard Wednesdays

Whiteboard Wednesdays—The Power of WiGig (802.11ad)

In this week's Whiteboard Wednesdays video, Bob Salem explains WiGig (IEEE 802.11ad…

• less than a min read
wireless , Whiteboard Wednesdays , interfaces , 802.11ad , wiGig

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Highlight Nets Associated with Component? It…

With the 16.6 Allegro PCB Editor release, a simplified method to highlight or de…

• less than a min read
PCB Layout and routing , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor

SoC and IP

Link Training: Establishing Link Communication Between DisplayPort Source and Sink…

Link training is the first stepping stone to enabling the communication channel between…

• 2 min read
Verification IP , VIP , DisplayPort , Link Training , Design IP and Verification IP

SoC and IP

ARM-Cadence IP Deal Propels Engineering Innovation Ahead: Martin Lund

On March 18, Cadence and ARM announced a groundbreaking deal that provides reciprocal…

• 6 min read
IP , electronic system design , cadence , systems engineering , IP design , ip cores , interoperability , ARM

Whiteboard Wednesdays

Whiteboard Wednesdays—Cognitive Layering Technique for Low-Energy, Sensor-Rich D…

In this week's Whiteboard Wednesdays video, Chris Rowen talks about techniques for…

• less than a min read
Whiteboard Wednesdays , IP , IoT , sensors , Tensilica , always-on , power

SoC and IP

Mobile World Congress: Two New Audio IP Announcements

BARCELONA, Spain—Mobile World Congress is not surprisingly focused on mobile devices…

• less than a min read
DTS , #MWC15 , cadence , audio , audio subsystems , Mobile World Congress , IP design , Tensilica , HiFi Audio , MaxxVoice

Whiteboard Wednesdays

Whiteboard Wednesdays—Major Enhancements of the PCIe Gen 4 Specification

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan talks about the…

• less than a min read
Whiteboard Wednesdays , IP , PCIe Gen4 , bandwidth , PCI Express , power

Life at Cadence

A Great Place to Do Great Work: Celebrating Our First Year on the FORTUNE List of…

Innovation starts with our people. For over 25 years, Cadence has been a leader…

• 4 min read
cadence , Fortune , GPTW , Lip-Bu Tan , Fortune 100 best companies to work for , great place to work

SoC and IP

IP Requirements for Verifying CHI-Based Designs

Just as IP components offload design effort, verification IP (VIP) components offload…

• 2 min read
Verification IP , Interconnect Validator , IVD , CHI , VIP , Design IP and Verification IP , CHI VIP

SoC and IP

Mobile World Congress: A Decade of Change in IP Innovation

BARCELONA, Spain—In the past decade, immense change has come to mobile electronic…

• 1 min read
electronic system design , #MWC15 , cadence , Steve Roddy , Mobile World Congress , Tensilica , mobile , IC design

Analog/Custom Design

Virtuosity: 12 Things I Learned In February by Browsing Cadence Online Support

Application Notes 1. Voltus-Fi Power Analysis Support and Power Grid View Generation…

• 3 min read
AMS Designer , PSPICE , Voltus , Layout , Constraints , FinFET , VLS XL

SoC and IP

WiGig Has Arrived to Enable IoT Designs--and Cut the HDMI Cord!

What is WiGig WiGig is the name given to a high-speed multi-gigabit wireless communications…

• 3 min read
wireless , cadence , IP blocks , IP design , WiGig IP , 802.11ad , wiGig , HDMI , WiFi

Whiteboard Wednesdays

Whiteboard Wednesdays - Optimizing Power Via a Configurable Processor

In this week’s Whiteboard Wednesdays, Chris Rowen takes a look at the basic energy…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , optimize power , Tensilica , energy , configurable processor , power

Analog/Custom Design

Virtuosity: 13 Things I Learned in January 2015 by Browsing Cadence Online Suppo…

'Tis the end of an era, folks. It should not be a surprise, but IC 5.1.41 reached…

• 2 min read
EAD , ADC , PLL , ADE , Spectre , Parasitic analysis
CDNS - Fix Layout Hompage