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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Analog/Custom Design

Virtuosity: 10 Things I Learned in March by Browsing Cadence Online Support

Topics in March include advanced analysis in ADE GXL, taking advantage of lots of…

• 2 min read
Analog Design Environment , Virtuoso IC6.1.5 , Virtuoso Space-based Router , Rapid Adoption Kit , IC615 , IC 6.1.5 , ADE , VLS GXL , Virtuoso Analog Design Environment , Monte Carlo , Virtuoso Layout Suite L , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , VLS L , AMS simulation , Custom IC Design , modgens , RAKs , Virtuoso Layout Suite , Virtuoso Layout Suite GXL , VLS XL , SKILL , Virtuoso Layout Suite XL

System, PCB, & Package Design 

Corral Your Selections with New Lasso and Path Modes in 16.6 APD and SiP

The level of ease and efficiency you experience in selecting the items needed for…

• 2 min read
package , SiP , IC Package , IC Packaging , packaging , Digital SiP design , 16.6 , APD , wirebonds , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , SiP Layout , wirebonding , IC Package Physical layout and co-design

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Generic Cross-Section Files? See for Yourself…

Beginning with the Allegro PCB Edito r 16.6 release, you are provided a methodology…

• 2 min read
PCB , PCB Layout and routing , ECSets , Constraint-driven PCB Design flow , constraint databases , Allegro GUI , Allegro 16.6 , electrical constraints , 16.6 , SPB , PCB Editor , Constraint Manager , Layout , design , "PCB design" , constraint difference , PCB design , Constraints , Grzenia , Allegro PCB Editor

Verification

Develop for Debugability – Part 1

Debugging is the most time-critical activity of any verification engineer. Finding…

• 4 min read
AF , Specman , debug , Functional Verification , encapsulate , aspect-oriented programming , encapsulating aspects , debugability , e language , Incisive Enterprise Simulator (IES) , debugging , simulation , verification , Daniel Bayer

System, PCB, & Package Design 

What's Good About RF PCB and Autoplace? 16.6 Has Many New Enhancements!

The 16.6 Allegro RF PCB application has many new enhancements. I’ll cover a few over…

• 5 min read
PCB , PCB Layout and routing , RF , Cadence Design Systems , Allegro RF SiP , Allegro 16.6 , RF PCB , autoplace , 16.6 , Placement Edit , SPB , PCB Editor , Design Entry HDL , design , PCB design , Design Entry , Grzenia , Allegro PCB Editor , Schematic

Analog/Custom Design

Unleashing Mixed-Signal Tech on Tours (ToTs) in North America

At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two…

• 2 min read
AMS , EDI , CDNLive , CDNLive 2013 , MS ToT , cadence , tech on tour , mixed-signal IP , AMS Designer , analog , analog behavioral models , analog/mixed-signal , Virtuoso , mixed signal methodology guide , mixed signal , CDNLive SV 2013 , OpenAccess , SoCs , AMS Verification , mixed-signal verification

Digital Design

Five-Minute Tutorial: Set Flip-Chip Bumps as Voltage Sources in EPS/EDI Rail Ana…

When running power and rail analysis for a flip chip, we used to have to spend some…

• 3 min read
EDI , rail analysis , EPS , Five-Minute tutorial , Power Analysis , flip chip , bump

Verification

Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of…

Great news.... Incisive Debug Analyzer (IDA) is one of five finalists for the EETimes…

• 2 min read
SystemVerilog , IDA: Functional Verification , ACE , Specman , Specman/e , cadence , debug , Specman e , Incisive Enterprise Simulator , Incisive Debug Analyzer , EDA , Incisive , e , Incisive Enterprise Simulator (IES) , simulation , IUS , EE Times

System, PCB, & Package Design 

What's Good About PCB SI and Vias? 16.6 Has Many New Enhancements!

In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more…

• 5 min read
PCB SI , PCB , SI , inset vias , Allegro 16.6 , cadence , Signal Intregrity , SigXP UI , 16.6 , PCB Signal and power integrity , layer stacks , "PCB SI" , Signal Integrity , via , design , "PCB design" , Design Reuse , PCB Signal integrity , Allegro PCB SI , Grzenia , SI analysis and modeling , Allegro

Analog/Custom Design

SKILL for the Skilled: Part 7, Many Ways to Sum a List

In this episode of SKILL for the Skilled I'll introduce a feature of the let primitive…

• 4 min read
Team SKILL , programming , Jim Newton , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

System, PCB, & Package Design 

Reduce Flip-Chip Design Time with Cadence Advanced Package Router (APR) for 16.6…

Perhaps the most time-consuming aspect to designing the package substrate for a large…

• 1 min read
IC Package , IC Packaging , Digital SiP design , Advanced Package Router , 16.6 , IC Packaging and SiP , APR , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , IC Package Physical layout and co-design

System, PCB, & Package Design 

Customer Support Recommended – Regulation Loop Design Using Allegro AMS Simulator…

Feedback regulation loops are widely used by power electronic designers. It is one…

• 3 min read
SPB16.3 , Allegro 16.6 , customer support , AMS simulator , closed loop design , 16.6 , Allegro 16.3 , Support , Allegro AMS , Allegro 16.5 , PSPICE , Appnotes , loop design , regulation loops , Appnote , feedback regulation loops , "PCB design" , open loop design , PCB design , 16.5 , AMS simulation , SPB16.5 , application note , Schematic

System, PCB, & Package Design 

What's Good About Allegro Package Designer (APD) Bond Wire "Text In?" You’ll Need…

Cadence IC Packaging tools today provide a spreadsheet-based import mechanism for…

• 2 min read
PCB , IC Packaging , Allegro 16.6 , cadence , 16.6 , APD , Wirebond , Allegro Package Designer , design , bond wires , Grzenia , die abstract , wire bond , Allegro

Analog/Custom Design

Virtuosity: 10 Things I Learned in February By Browsing Cadence Online Support

February was a big month for RAKs (Rapid Adoption Kits)! If you haven't checked out…

• 3 min read
AMS , APS , Virtuoso Advanced Node , Virtuoso IC6.1.5 , IC 6.1 , Rapid Adoption Kit , Analog Simulation , Advanced Node , IC615 , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , variability , Spectre , Analog Design Environment , ADE-XL , Virtuosity , Custom IC Design , RAKs , Virtuoso Layout Suite GXL

Verification

What to See at the DATE Conference: High-Level Synthesis

The DATE (Design Automation and Test in Europe) Conference is next week (March 18…

• 1 min read
High-Level Synthesis , DATE , Alex Kondratyev , C-to-Silicon Compiler , HLS , system-level , ESL , QoR , System Design and Verification

Verification

Specman: Getting Source Information on Macros

When you write a define-as or define-as-computed e macro, you sometimes need the…

• 2 min read
AF , Specman , Functional Verification , source information on macros , e language , team specman , macros , messages

Verification

DVCon 2013: Functional Verification Is EDA’s “Killer App”

With another year of record attendance, DVCon has again proven that a functional…

• 3 min read
Joe Hupcey III , Specman , methodology , Team Verify , DVCon 2013 , metric driven verification (MDV) , Functional Verification , Formal Analysis , UVM e , Specman e , formal , formal apps , Richard Goering , e code , e , e language , DVcon , apps , papers , metrics , verification

Digital Design

CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance…

Implementing SoCs with embedded processors at advanced nodes has become increasingly…

• 5 min read
ARMv8 , EDI , Low Power , Cortex-A15 , CDNLive , Cortex-A57 , Cortex-A7 , RC-Physical , NVIDIA , Avago , SoC , ccopt , digital , GigaOpt , Digital Implementation , Encounter Digital Implementation , AppliedMicro , high performance , CDNLive Silicon Valley , ARM , CDNLive! Cadence

Verification

System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and…

Ever since switching from being a hardware/software chip developer to being an enabler…

• 4 min read
AVIP , Intel , Verification IP , RPP , Low Power , Verification Computing Platform , Virtual System Platform , Fast Models , PXP , CDNLive , cadence , Acceleration , Teledyne LeCroy FPGA Based Prototyping , System to Silicon Verification , AMD , Dynamic Power Analysis , System Design and Verification , System Development Suite , Samsung , embedded software , VSP , Incisive , Palladium XP , Emulation , Imperas , Freescael , Bluespec , CDNLive! , ARM , Schirrmeister , Accelerated Verification IP , low power optimization , VCP
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