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Featured

Corporate News

DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

Every year, Design Automation Conference (DAC) brings big announcements, packed demos…

Corporate
Corporate 7 Aug 2026 • 5 min read
Jasper Formal Verification Platform , featured , agentic ai , DAC 2026 , AI for design

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
Corporate 31 Jul 2026 • 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
Corporate 27 Jul 2026 • 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
Corporate 26 Jul 2026 • 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

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  • SoC and IP 437
  • System, PCB, & Package Design  1020
  • Verification 1338
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  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Pastemask DRC? 16.6 Has Several New Enhancements…

The Allegro PCB Editor 16.6 Pastemask to Pastemask DRC now checks the ‘Package Geometry…

Jerry GenPart 28 Sep 2015 • less than a min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

SoC and IP

Cadence Announces the First MIPI I3C Verification IP!

The MIPI Alliance has developed dozens of specifications, standardizing all interfaces…

Moshik Rubin 23 Sep 2015 • 1 min read
Verification IP , MIPI Alliance , MIPI , Design IP and Verification IP

Whiteboard Wednesdays

Whiteboard Wednesdays - A Peek Inside Future Automotive Networks

In this week's Whiteboard Wednesdays video, Charles Qi explains future automotive…

References4U 22 Sep 2015 • less than a min read
Whiteboard Wednesdays , automotive engineering , Automotive Ethernet , automotive electronics , automotive IP

Life at Cadence

Cadence Celebrates Women’s Day in India

Cadence India celebrated Women’s Day across all four sites on March 9th. Women’s…

llightbody 15 Sep 2015 • less than a min read
Insights on Culture , inclusion , Women's Day , HeforShe , Cadence India

Whiteboard Wednesdays

Whiteboard Wednesdays - Why a DSP is the Right Choice for Imaging and Vision Alg…

In this week's Whiteboard Wednesday's video, the third in a three-part series, Pulin…

References4U 15 Sep 2015 • less than a min read
DSP , Whiteboard Wednesdays , IP , vision algorithms , Tensilica , imaging algorithms

Verification

Incisive vManager Free Video Training

The Incisive vManager tool for professional verification planning and management…

John Brennan 15 Sep 2015 • 2 min read
Functional Verification , Cadence Online Support , Incisive , training , vManager

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Replace Padstack? 16.6 Has Several New Enhancements…

The Allegro PCB Editor 16.6 ‘ Replace Padstack ’ command is now available as a context…

Jerry GenPart 15 Sep 2015 • less than a min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro 16.6 , Routing , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

System, PCB, & Package Design 

Generate Daisy Chain Patterns for Test Vehicles and Other Applications Using the…

With increasing design complexity comes the need to create test vehicles to qualify…

ICPackagingPro 11 Sep 2015 • 5 min read
Co-Design , 16.6 , manufacturing , early adopter , SiP Layout , substrate design tools , Physical layout and co-design , daisy chain

Whiteboard Wednesdays

Whiteboard Wednesdays—DSP for Automotive Applications

In this week's Whiteboard Wednesday's video, Charles Qi discusses how Cadence scaleable…

References4U 8 Sep 2015 • less than a min read
Automotive , DSP , Whiteboard Wednesdays , IP , Tensilica

Verification

Accelerating the Next Big Shift in Verification

Today Cadence announced that we are aligning our proposal to the Accellera Portable…

fschirrmeister 8 Sep 2015 • 5 min read
pswg , scenario , UML , software-driven verification , Accellera

Whiteboard Wednesdays

Whiteboard Wednesdays - Addressing SoundWire Design Challenges

In this week's Whiteboard Wednesdays video, the second in a two-part series, Charles…

References4U 1 Sep 2015 • less than a min read
Design IP , Whiteboard Wednesdays , software design challenges , MIPI SoundWire

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Line Width Retention? 16.6 Has It!

Currently, user line width overrides are permitted during the Add Connect command…

Jerry GenPart 1 Sep 2015 • 1 min read
PCB Layout and routing , 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro

System, PCB, & Package Design 

Integrate PVS into Your IC Package Design Flow to Optimize for Manufacturability…

As package substrates continue to get more complex, often resembling silicon as much…

ICPackagingPro 28 Aug 2015 • 4 min read
IC Packaging and SiP Design , GDSII , DRC , stream , 16.6 , SPB , PVS

SoC and IP

USB Type-C Ecosystem, Issues, and Opportunities

USB Type-C is an innovation that is transforming the electronics industry. What is…

Steve Brown 26 Aug 2015 • less than a min read
USB Type-C , DisplayPort , MCCI , Alternate Mode

Whiteboard Wednesdays

Whiteboard Wednesdays—The Applications and Benefits of 802.11ad

In this week's Whiteboard Wednesdays video, Bob Salem provides a detailed overview…

References4U 25 Aug 2015 • less than a min read
wireless , Whiteboard Wednesdays , 802.11x , 802.11ad

Digital Design

Five-Minute Tutorial: Innovus Clock Tree Synthesis and Debugger

Hi Everyone, Last time, our Five-Minute Tutorial focused on the new Innovus Placement…

Kari 21 Aug 2015 • less than a min read
training , ccopt , clock tree synthesis , debugger , Digital Implementation , Innovus

SoC and IP

Cadence IP for USB Works over Type-C (Proof Inside)

There is no other specification in the history of USB that caused so much discussion…

Jacek Duda 20 Aug 2015 • 1 min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of Automotive Electronics

In this week's Whiteboard Wednesdays, Charles Qi talks about the evolution of electronics…

Christine Young 18 Aug 2015 • less than a min read
Whiteboard Wednesdays , IP , functional safety , infotainment , automotive electronics , Tensilica , ADAS

System, PCB, & Package Design 

What's Good About Allegro PCB Editor NC Route? 16.6 has Several New Enhancements…

There are a few NC Route enhancements in the 16.6 Allegro PCB Editor release. Read…

Jerry GenPart 18 Aug 2015 • 1 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , Routing , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro
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