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Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Artificial Intelligence (AI)

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design
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Blog - Post List
Latest blogs

Verification

Video Easter Egg: Incisive Formal Verifier and SVA driving a Rubik's Cube robot

Just in time for Easter, Team Verify's Apurva Kalia, Manu Chopra, and Suman Ray of…

• 1 min read
Suman Ray , ABV , Apurva Kalia , Formal Analysis , Easter , formal , Manu Chopra , SVA , Verilog , Lego , assertions , egg , robot , ARM , IEV , Rubik's Cube , Formal verification , IFV , Assertion-based verification

Verification

Can DRAM Contents Survive a Reboot? Surprisingly, In Most Cases The Answer is, “Yes…

A Cadence DRAM Memory Controller IP customer asks, "I have a DRAM subsystem with…

• 3 min read
controller IP , security , IP , Princeton , Memory , VIP , encryption , SoC , memory IP , DRAM , Denali , DDR , reboot , MMAV

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Flipping and Origins? Look to SPB16.3 and See

There are a couple quick new SPB16.3 Allegro PCB Editor features to mention this…

• 2 min read
PCB , PCB Layout and routing , SPB16.3 , flipping , SPB 16.3 , flip design , PCB Editor , Layout , design , "PCB design" , PCB design , Allegro PCB Editor , Allegro

Analog/Custom Design

Analog IP Verification - A Reference Guide to Practices Used

I have had a lot of discussions recently around improving the final integration of…

• 1 min read
AMS , Analog Design Environment , mixed-signal simulators , Analog Simulation , analog , IC 6.1.5 , ADE , assertion , AMS simulation , assertions , mixed signal

Analog/Custom Design

Will Evolving Language Standards Address Mixed-Signal Verification Problems?

Mixed-signal verification has been one of the hottest topics in the past year, and…

• 6 min read
SystemVerilog , AMS , assertion-based , SV-DC , analog , ADE , Mixed-Signal , SVA , DMS , Accellera , mixed signal , A-SVA

System, PCB, & Package Design 

What's Good About Capture CIS Relational Tables? SPB16.3 Has a Few New Enhancements

If you have defined relational fields in your Allegro Design Entry CIS configuration…

• 2 min read
SPB16.3 , Allegro Design Entry , data management , Design Entry CIS , OrCAD Capture , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , relational tables , design data management , design , OrCAD , Component Information Portal (CIP) , Librarians , library , PCB Capture , Schematic

Analog/Custom Design

Virtuoso IC 5.1.41 Was Good but Virtuoso IC 6.1 is Better

With the recent release of unified custom/analog flow that is based on the latest…

• 3 min read
Analog Design Environment , Virtuoso IC6.1.5 , IC 6.1 , analog , Constraint-driven , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Custom IC Design , SKILL++ , SKILL

Verification

NEW Enterprise Planner Videos!

Videos on Enterprise Planner: What's it worth to you? Submitted By MDV…

• 1 min read
videos , Verification methodology , Functional Verification , Metric Driven Verification , vPlan , verification planning , Enterprise Manager , Enterprise Planner , Plan and metrics management , MDV

Digital Design

Encounter Quick Tip: How to Repair Command Line Navigation When Launching via bs…

When two users report the same issue in the same week I'm glad I can share the problem…

• 1 min read
EDI , encounter , Digital Implementation , Encounter Digital Implementation , command line , bsub

SoC and IP

New Memory Technologies, New Possibilities

As a complete gadget geek, it’s always exciting to play with the latest technological…

• 1 min read
controller IP , Design IP , IP , Memory , DDR4 , wide i/o , SoC , storage , Denali , DDR , SoC Realization , Wide-IO

Verification

Combating System-Level Design Confusion

I would like to add my thanks to Gary Smith for his short "Industry Note" titled…

• 5 min read
silicon virtual prototype , virtual platforms , software virtual prototype , TLM , virtual prototypes , architectural , embedded software , Gary Smith , System-Level Design , architects workbench , SystemC , C++ , ESL , System Design and Verification

Verification

1st Anniversary of the Team Verify Blog!

Verifiers rejoice: today is the 1st anniversary of the launch of this blog!!! To…

• 3 min read
workshops , NextOp , Low Power , ABV , methodology , Zocalo , metric driven verification (MDV) , Functional Verification , Formal Analysis , vPlan , ABVIP , formal , Coverage-Driven Verification , SoC , Kit , Chris Komar , Oski Technology , assertion synthesis , metric-driven verification , Twitter , assertions , SoC Connectivity , MDV , IEV , simulation , Formal verification , IFV , blog , Assertion-based verification

Verification

Video: Update on AMIQ’s DVT IDE and UVM 1.0 at DVCon 2011

The UVM 1.0 release was the big story of DVCon 2011, as it's the first verification…

• 1 min read
uvm , methodology , Functional Verification , Amitroaie , OVM , OVM e , e , DVT , ecosystem , DVcon , AMIQ , eRM , IDE , IES-XL

Verification

Why Can’t You Write My Assertions for Me? - Part 1

As regular readers know from previous posts , I have a lot of background in assertion…

• 3 min read
conformal , NextOp , ABV , Functional Verification , formal , CPF , CDC , Palladium , Incisive , assertion synthesis , assertions , Constraints , IEV , Formal verification , IFV , Assertion-based verification

System, PCB, & Package Design 

What's Good About ADW’s Configuration Manager? Check out the ADW16.3 Release and

The ADW16.3 Allegro Design Workbench has a new Configuration Manager that simplifies…

• 1 min read
PCB , SPB16.3 , Allegro 16.3 , SPB 16.3 , Allegro Design Workbench , Library flow , Library and design data management , PCB Editor , design data management , design , Design Entry , ADW 16.3 , Librarians , library , PCB Capture , Schematic

Verification

Video: Formal Verification Service Provider Oski Technology at DVCon 2011

While there was a lot (justifiable) buzz around the UVM 1.0 release, formal and assertion…

• 1 min read
ABV , verification strategy , Functional Verification , Formal Analysis , ABVIP , formal , Oski Technology , DVcon , IEV , Formal verification , IFV , verification

System, PCB, & Package Design 

What's Good About PCB PI Discontinuity Modeling? See For Yourself in SPB16.3!

The current Allegro PCB Power Integrity (PI) tool is fast, but not accurate enough…

• 1 min read
PCB SI , PCB , SI , PI , SPB16.3 , Integrity Check , discontinuity modeling , PCB PI , Signal Intregrity , SigXP UI , SPB 16.3 , Power Integrity , High Speed , PCB power integrity , SPB , electromagnetic , PCB Signal integrity , Allegro PCB Editor , SI analysis and modeling , Allegro

RF Engineering

My Favorite nport Settings for Spectre and SpectreRF

The nport component located in analogLib can be used in circuits for Spectre and…

• 4 min read
nport , RF , RF Simulation , Circuit simulation , RFIC , Spectre RF , Analog Simulation , nport settings , Spectre , analogLib

System, PCB, & Package Design 

What's Good About Allegro PCB Editor 3D Viewing? Oh My – Check Out SPB16.3!

The SPB16.3 Allegro PCB Editor has a new 3D Viewer! Viewing a 3D rendering of the…

• less than a min read
PCB , PCB Layout and routing , SPB16.3 , mechanical parts , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Layout , design , "PCB design" , PCB design , Allegro PCB Editor , 3D viewer , Allegro
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