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Verification

Verifying AMBA® 4 ACE Designs – Cadence is Ready to Help, Now

ACE is here. Are you ready? Designers of multimedia smartphones, tablets, and other…

PeteHeller 15 Aug 2011 • 1 min read

Verification IP , ACE , Functional Verification , VIP , tablet , AMBA , Smartphone , EE Times

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 1

In the previous couple of SKILL for the Skilled postings, we looked at some of the…

Team SKILL 15 Aug 2011 • 3 min read

Sodoku , Team SKILL , programming , classes , object orientation , Virtuoso , object system , Lisp , Custom IC Design , SKILL++ , SKILL , Allegro

Verification

IP Cannot be an Efficient Abstraction Level Without SystemC!

EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction…

Jack Erickson 12 Aug 2011 • 3 min read

High-Level Synthesis , IP , TLM , RTL , abstraction , IP re-use , EDN , SoC , IP assembly , system design , SystemC , HLS , System Design and Verification

RF Engineering

Measuring Fmax for MOS Transistors

The following question has come up in comments: "How do I measure F max for an MOS…

Art3 11 Aug 2011 • 3 min read

RF , RF Simulation , analog/RF , Circuit simulation , RFIC , bipolar transistor , MOS transistors , measuring Fmax , Virtuoso , Fmax , RF design , fmax testbench , simulation , bsim3v3

Digital Design

Five-Minute Tutorial: The Encounter Digital Implementation Cell Viewer

How many times have you wanted to look at a certain standard cell in the Encounter…

Kari 10 Aug 2011 • 1 min read

EDI , Layout Control , encounter , EDI 10.1 , Digital Implementation , five minute tutorial , Cell Viewer

Verification

Virtual Flash Memory Gets Real

This week's Flash Memory summit will not only highlight the IP Cadence delivers,…

Steve Brown 8 Aug 2011 • 1 min read

Virtual System Platform , IP , Memory , virtual platforms , TLM , virtual prototypes , TLM 2.0 , flash memory , Incisive Software Extensions , ISX , Flash Memory Summit , System Design and Verification

System, PCB, & Package Design

What's Good About Retaining Electrical Constraints? Look to SPB16.5 and See!

Currently, many of the SPB products support extended nets, better known as Xnets…

Jerry GenPart 8 Aug 2011 • 8 min read

PCB SI , PCB , PCB Layout and routing , IC Packaging and SiP Design , SI , ECSets , Allegro Design Entry , Constraint-driven PCB Design flow , diff pairs , Design Rule Checker , Routing , Signal Intregrity , DEHDL , Analog and RF SiP design , Digital SiP design , electrical constraints , SigXP UI , PCB Signal and power integrity , High Speed , APD , PCB power integrity , Allegro Design Workbench , Allegro 16.5 , PCB Editor , Design Entry HDL , advanced package designer , ASA , Layout , Allegro System Architect (ASA) , Xnets , Front-end PCB design , design , PCB Signal integrity , Allegro PCB SI , PCB design , Design Entry , SPB16.5 , Allegro PCB Editor , differential pairs , SI analysis and modeling , Differential Pair Support , ConceptHDL , Schematic , Allegro

RF Engineering

Guidelines for Setting Pnoise/HBnoise Sidebands to Get Accurate Results

I get quite a few questions from designers along the lines of "How do I set the number…

Tawna 5 Aug 2011 • 2 min read

RF , RF Simulation , analog/RF , HBnoise , shooting newton , HB , Spectre RF , pnoise , RF spectre spectreRF , spectreRF , RF design , harmonic balance , pss

Verification

A Must Read: the ARM Cortex-A Programmer's Guide

For the last couple of years, I have been getting a lot of e-mail from different…

jasona 4 Aug 2011 • 2 min read

ARM Cortex-A , virtual platforms , programmer's guide , virtual prototypes , Cortex-A , virual platform , ARM Architecture , ARM , linux , System Design and Verification

SoC and IP

Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features

Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI…

archive 3 Aug 2011 • 1 min read

controller IP , Design IP , IP , PCI Express 3.0 , Gen3 , video , PCIe , PCIe Gen3 , SR-IOV , PCI Express

System, PCB, & Package Design

What's Good About PCB SI Design Setup and Audit? 16.5 Has MANY New Enhancements!

Many of the problems that customers encounter today when running a signal integrity…

Jerry GenPart 2 Aug 2011 • 10 min read

PCB SI , IC Packaging and SiP Design , SI , SiP , Signal Intregrity , SigXP UI , PCB Signal and power integrity , "PCB SI" , Allegro 16.5 , PCB Editor , "PCB design" , Allegro PCB SI , PCB design , SPB16.5 , SI analysis and modeling

Verification

The Return of the Son of Real-World Assertions

I've received some nice feedback on my previous two posts about real-world situations…

tomacadence 1 Aug 2011 • 3 min read

ABV , Functional Verification , formal , assertions , Assertion-based verification

Analog/Custom Design

Virtuoso Analog Design Environment XL – Data Everywhere, But You Have a Review in…

In my previous blogs , I talked about productivity enhancing features of Virtuoso…

archive 29 Jul 2011 • 2 min read

analog , ADE , Virtuoso , Analog Design Environment , Virtuoso datasheets , Schematic Editor , Custom IC Design , datasheets

SoC and IP

Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller…

This video is part one of a two-part series demonstrating the Cadence PCI Express…

archive 28 Jul 2011 • less than a min read

Design IP , IP , Gen3 , video , PIPE , SAS RAID , PCIe , PCI Express Gen3 , PCI , PCI Express , PCI-SIG

Verification

Four Uses for the Venerable Virtual Platform UART

The Universal Asynchronous Receiver/Transmitter (UART) is one of the oldest hardware…

jasona 27 Jul 2011 • 2 min read

System, PCB, & Package Design

What's Good About APD’s Assembly DRCs? You’ll Need the 16.5 Release to See!

Prior to the Allegro Package Designer (APD) 16.3 release, Design Rule Check (DRC…

Jerry GenPart 26 Jul 2011 • 25 min read

PCB , PCB Layout and routing , IC Packaging , DRC , APD , ADRC , Allegro 16.5 , SPB , PCB Editor , advanced package designer , Layout , assembly DRCs , "PCB design" , PCB design , SPB16.5 , Allegro

Verification

ARM Generic Interrupt Controller HOWTO

Way back in 2004, I wrote a book called Co-Verification of Hardware and Software…

jasona 22 Jul 2011 • 5 min read

Virtual System Platform , Cortex-A9 , System Design and Verification , Cortex-A , howto , ARM Generic Interrupt Controller , SystemC , GIC , ARM , Wadikar , Generic Interrupt Controller

Verification

Some Reflections on the Development of UVM World

In a recent blog post , I celebrated our donation of the Cadence-developed UVM…

tomacadence 22 Jul 2011 • 3 min read

uvmworld.org , uvm , uvm world , Functional Verification , OVM , universal verification methodology , Accellera , verification

Verification

Video: Discussion with EET’s Brian Fuller on EDA, Engineers, and Social Media

At DAC I had the honor of being interviewed by EE Times editor Brian Fuller on my…

jvh3 21 Jul 2011 • 1 min read

Brian Fuller , DAC , Joe Hupcey III , tweeting , videos , interview , Blogging , YouTube , blogs , Facebook , OrCAD , CtoSilicon , Twitter , Social Media , EE Times , DAC360

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