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Enterprise Planner - CSV Import Tech Tip

Are you interested in an automating your directed or random test list that you manually…

Team MDV 15 Jul 2011 • 1 min read

metric-driven , Functional Verification , Metric Driven Verification , CSV , vPlan , tech tips , EDA360 , Incisive , Enterprise Manager , Enterprise Planner , MDV , Excel , verification

Verification

Creating SystemC TLM-2.0 Peripheral Models

Over two years ago, I made some experiments and raised some requirements for an effective…

TeamESL 14 Jul 2011 • 8 min read

Virtual System Platform , virtual platforms , TLM , IP-XACT , Models , virtual prototypes , System Design and Verification , TLM 2.0 , embedded software , VSP , TLM-2.0 , Team ESL , peripheral , SystemC , ESL

Digital Design

Five-Minute Tutorial: Finding EDI Videos

I've seen a few requests in the forums asking about EDI videos. Today I will show…

Kari 14 Jul 2011 • less than a min read

COS , EDI , video , encounter , Digital Implementation , five minute tutorial , 5 minute tutorial

System, PCB, & Package Design

What's Good About Allegro GRE Route Around Etch Shapes? See For Yourself in 16.5

This new 16.5 Global Route Environment ( GRE ) functionality was designed to allow…

Jerry GenPart 13 Jul 2011 • 1 min read

PCB , PCB Layout and routing , global route , Routing , Allegro 16.5 , SPB , PCB Editor , Layout , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , GRE , etch shapes

Verification

More Examples of Missing Real-World Assertions

Back in May, I published a blog post with examples of real-world situations that…

tomacadence 12 Jul 2011 • 3 min read

ABV , asssertion-based verification , Functional Verification , formal , assertions

Analog/Custom Design

Things You Didn't Know About Virtuoso: Viva ViVA!

I realize that I have been quite remiss in that I have not yet blogged about the…

stacyw 8 Jul 2011 • 1 min read

Analog Design Environment , ViVa-XL , Virtuoso IC6.1.5 , Analog Simulation , IC 6.1.5 , Virtuoso Analog Design Environment , Virtuoso , ViVA , ADE-XL , Custom IC Design

Verification

Celebrating the Success of the UVM World Web Site

In case you missed it, Cadence issued a press release last week announcing that we…

tomacadence 6 Jul 2011 • 2 min read

uvm , uvm world , universal verification methodology , Accellera

Analog/Custom Design

Synchronizing Designs and Behavioral Models in Mixed-Signal Flows

The creation of behavioral models is only one part of the process of using those…

Paul Foster 6 Jul 2011 • 3 min read

AMS , Virtuoso-AMS , mixed signal design , AMS-Designer , amsDMVAMS-Designer , Verilog-AMS , analog , Mixed-Signal , model validation , mixed signal , wreal

Verification

True Stories of Assertion Driven Simulation (ADS) in the Wild

Ever since Assertion-Driven Simulation (ADS) became available, I have been working…

TeamVerify 4 Jul 2011 • 4 min read

AXI , ABV , Verification methodology , Functional Verification , Formal Analysis , ABVIP , formal , simvision , VIP , ADS , DDR , Club Formal , Constraints , IEV , Assertion-Driven Simulation , Formal verification , Assertion-based verification

SoC and IP

Cadence Demonstrates PCI Express 3.0 Controller IP in Customer Silicon

At the June 2011 PCI-SIG Developer's Conference, Cadence demonstrated Cadence Design…

archive 30 Jun 2011 • less than a min read

controller IP , Design IP , PCI Express 3.0 , Gen3 , PIPE , PCI , PCI-SIG

Verification

Video: Distinguished Engineer Mike Stellfox on UVM, the Debug Bottleneck, and System…

My colleague and Cadence Distinguished Engineer Mike Stellfox leads a group of trailblazers…

jvh3 29 Jun 2011 • less than a min read

DAC , uvm , debug , system realization , Mike Stellfox , Accellera , SystemC , Trailblazer

System, PCB, & Package Design

What's Good About Allegro PCB Router Region Rules? 16.5 has a few new enhancements

Designers normally create nets or groups of nets to assign constraints. This leads…

Jerry GenPart 29 Jun 2011 • 1 min read

PCB , PCB Layout and routing , Constraint-driven PCB Design flow , global route , Routing , Allegro 16.5 , PCB Editor , Layout , design , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , Allegro

Verification

Before DAC, There Was Club Formal – An Event Series Completely Focused on Formal…

To complement our support of DAC, CDNLive, and other large-scale events, where the…

TeamVerify 28 Jun 2011 • 1 min read

events , ABV , verification strategy , Functional Verification , Formal Analysis , formal , Incisive , Incisive Seminar , ADS , Oski Technology , Silicon Realization , assertions , Club Formal , ClubT , IEV , Assertion-Driven Simulation , Formal verification , IFV , verification , Assertion-based verification

Analog/Custom Design

M/S Technology on Tour Blog – Model Validation and Assertion Based Verification

In February 2011, I had the opportunity to meet a group of analog and mixed-signal…

PrabalB 28 Jun 2011 • 5 min read

Virtuoso-AMS , mixed-signal ToT , amsDMVAMS-Designer , Mixed-Signal , SVA , model validation , Virtuoso , PSL , assertions , mixed signal

Verification

Full Sequence Coverage in a Single Line of e Code?

I was asked recently about how to easily collect coverage on the sequences generated…

teamspecman 28 Jun 2011 • 1 min read

Specman , e , OVM-e , e language , team specman , specman elite , AOP

Digital Design

Five-Minute Tutorial: Save Time With The Right Mouse Button

How many times have you done this: you want to flip or rotate a cell in your design…

Kari 27 Jun 2011 • 1 min read

EDI , right mouse button , encounter , Digital Implementation , rotate cell , five minute tutorial , flip cell , RMB , 5 minute tutorial

System, PCB, & Package Design

Advances in Leadframe Packaging Lead Cadence and CDS to Collaboration

One thing is certain about IC Package technology -- things change quickly. Leadframe…

TeamAllegro 27 Jun 2011 • 2 min read

Verification

Video: Duolog at DAC 2011 Update – Automating Design and Verification IP Integra…

One of the key tenants of the EDA360 vision is the need for scalable, correct-by…

jvh3 26 Jun 2011 • 1 min read

Cadence Connections , DAC , uvm , Virtual System Platform , IP , videos , IP-XACT , TLM 2.0 , VIP , EDA360 , Duolog , Incisive , Socrates , AMBA , ARM , David Murray

Verification

Video: DAC 2011 Update From NextOp CEO Yunshan Zhu

At DAC 2011 I had the opportunity to reconnect with Yunshan Zhu, the CEO of NextOp…

jvh3 23 Jun 2011 • less than a min read

Cadence Connections , NextOp , DAC , uvm , ABV , Yunshan Zhu , verification strategy , Functional Verification , Formal Analysis , BugScope , assertion synthesis , assertions , Design Automation Conference , Formal verification , verification , Assertion-based verification

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