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Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan
• 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform

Corporate News

Don’t Miss the 2025 North America Open Meeting!

Join Visionaries, Discover Breakthrough Tech, and Power Your Next Big Idea Are you…

Corporate
• 1 min read
featured , innovation , Beta CAE , event , AI

Corporate News

Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

A Look Back On 2009 (Before Hazarding Predictions For 2010)

Before I gaze into a crystal ball and add to the many fine predictions already made…

• 3 min read
SystemVerilog , metric driven verification (MDV) , Functional Verification , C , EDA , e , multi-language , coverage driven verification (CDV) , SystemC , MDV , ESL

System, PCB, & Package Design 

What's Good About SiP Layout ADRC? See For Yourself Using The SPB16.3 Release!

In the SPB16.3 release, the SiP Layout Assembly Design Rules Checker (ADRC) User…

• 16 min read
SiP , DRC , SPB 16.3 , ACSET , ADRC , PCB design

Verification

Why UVM Does Not Equal OVM Plus VMM

In the numerous tweets, blog posts, and online forum discussions on the upcoming…

• 1 min read
uvm , methodology , Functional Verification , OVM , compatibility , Accellera , OVM 2.1 , VMM

Verification

Methodology Is Important But Language Matters - Part 1

Historical trends in languagesMany of us have traveled around the world, and while…

• 3 min read
Verification planning and management , TLM , virtual platform , System Design and Verification , ESL High Level Synthesis , OVM , ASIC/ASSP , ANSI-C , C-to-Silicon , virtual prototype , C program , OSCiI , TLM 2.0-driven design , planning and management , ESL

SoC and IP

The Evolving Enterprise SSD: Gartner’s Forecasts

By Steve Leibson for Denali Software The appearance of SSDs into the storage…

• 5 min read

SoC and IP

SSD Interfaces and Performance Effects

By Steve Leibson for Denali Software IDC ’s Research Director John Rydning…

• 4 min read

SoC and IP

SSD and HDD Economic Forecast: Analyst Jim Handy Speaks Out

By Steve Leibson for Denali Software If you’re waiting for solid-state drives…

• 3 min read

Verification

Scalability Made OVM The Ideal Choice For UVM

The popularity of OVM that made it the idea choice for Accellera's UVM is rooted…

• 1 min read
performance , SystemVerilog , uvm , OVM ML , Functional Verification , OVM , e , Simulation acceleration , MDV

Analog/Custom Design

Things You Didn't Know About Virtuoso: Options? What Options?

Recently, I got involved in helping out a customer who had become frustrated using…

• 1 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , IC 6.1.4 , Custom IC Design

Verification

Q&A With Nick Heaton: Accelerating Verification Methodology and Tool Adoption

TeamMDV: Have you ever wondered why EDA Vendors don't make it easier for our customers…

• 5 min read
workshops , IPCM , methodology , Verification methodology , metric driven verification (MDV) , Functional Verification , Incisive , Enterprise Manager , Plan and metrics management , MDV

Verification

Tech Tip: Waving Specman Objects in SimVision

Did you know that you can wave Specman objects in IES-XL *and* also save the wave…

• 1 min read
Specman , debug , Functional Verification , simvision , e , IES-XL

SoC and IP

The End of NAND Flash as we Know It: Micron’s Dean Klein and Samsung’s Tony Kim Look…

By Steve Leibson for Denali Software Today, NAND Flash is king of the semiconductor…

• 3 min read

Digital Design

Encounter Screencast: Editing Wires More Quickly With Bindkeys

The Encounter Digital Implementation System offers interactive wire editing capabilities…

• 1 min read
Wire Editor , encounter digital implementation system , Digital Implementation , bindkeys

System, PCB, & Package Design 

What's Good About SigXp UI Changes? SPB16.3 Has Many New Enhancements!

The SPB16.3 SigXP UI has been enhanced to focus on giving users better access to…

• 8 min read
SigXP UI , layer stacks , SPB 16.3 , PCB design , Allegro

Digital Design

Sometimes It's The Little Things: Working With Square Brackets in Encounter

Good news! A long-standing source of irritation for Encounter users has been addressed…

• 1 min read
Ease of Use , Encounter Digital Implementation System 8.1

Verification

Android System Verification Part 6

Welcome to Part 6 of Android System Verification. It's getting hard to trace back…

• 3 min read
emulator , android , System Design and Verification , system

RF Engineering

Using The Composite Triple Beat Source to Speed up QPSS Analysis

Say you have a design with 4 input frequencies: 3164M (vco), 1449M (tone0), 1456M…

• 2 min read
RFIC , QPSS Analysis , CTB , Virtuoso Spectre , Spectre RF , MMSIM , RF Block Simulation , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , spectreRF , RF design , harmonic balance , Composite Triple Beat

SoC and IP

The Flash Factor for Consumer Devices: Will NAND Flash and Hard Disk Storage Coexist…

By Steve Leibson for Denali Software If you spend a lot of time reading and…

• 4 min read

Verification

Changing The "F" in RTFM to "Fantastic"

Talk about unsung -- tech writers just don't get the credit they deserve. They sit…

• 1 min read
Tech Pubs , Functional Verification , Incisive , Kit , IES , IES-XL
CDNS - Fix Layout Hompage