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Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan
• 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform

Corporate News

Don’t Miss the 2025 North America Open Meeting!

Join Visionaries, Discover Breakthrough Tech, and Power Your Next Big Idea Are you…

Corporate
• 1 min read
featured , innovation , Beta CAE , event , AI

Corporate News

Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About the SPB16.3 Release? Join The Virtual Conference 12/02/09 and See

You will NOT want to miss this event! The first ever Virtual Trade Show for the SPB…

• 4 min read
PCB , IC Packaging and SiP Design , Virtual Conference , SPB 16.3 , Allegroro , OrCAD , PCB design

Analog/Custom Design

Things You Didn't Know About The Rhinovirus and ViVA (Part 3)

Okay, so I really have no idea how to tie those 2 things together, but I ran across…

• 3 min read
ViVa-XL , IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Verification

Interview With Teradyne on Metric Driven Verification

Welcome to the first TeamMDV blog. We are excited to bring you information, tips…

• 3 min read
Functional Verification , Incisive , SoC , Enterprise Manager , Enterprise Planner , MDV , IES

Verification

Android System Verification Part 2

In Part 1 of this series on Android System Verification I provided the basics about…

• 3 min read
android , System Design and Verification , Java , ISX , Monkey

Verification

We and Our Competitors Agree (Well, Almost!)

It’s rare in EDA to see competitors agreeing, but an interesting article in EEtimes…

• 2 min read
DAC , ICE , System Design and Verification , Palladium , SoC , FPGA

System, PCB, & Package Design 

What's Good About Cadence Online Support? – Here’s My List!

My good friend and fellow blogger - Bob Dwyer - recently posted on the new Cadence…

• 2 min read
Support , PCB design , Online Support

Verification

IntelliGen Lab Now Live on Xuropa - See What You Are Missing!

Team Specman guesstimates that a majority of users have migrated to "IntelliGen"…

• 2 min read
IntelliGen , Specman , Functional Verification , Cadence VIP portfolio , e , DVcon , Xuropa , IES-XL

Verification

Android System Verification Part 1

From time to time I hear or read stories about how engineers find ways to apply Specman…

• 5 min read
Specman , android , System Design and Verification , Virtual Platforms , verification

Verification

Ten Things I've Learned About Formal

2009 is the tenth year that I've spent at least a portion of my time responsible…

• 2 min read
verifier , Enterprise , Functional Verification , formal , Incisive , IEV

Verification

"ClubT" Herzelia Israel Verification Seminar Invitation 17 November

Specmaniacs Based In Israel, Please join us for a day of in-depth presentations and…

• less than a min read
IntelliGen , Specman , verification strategy , Verification methodology , OVM ML , Functional Verification , simvision , VIP , OVM e , e , Enterprise Manager , Enterprise Planner , ClubT , IES-XL

Digital Design

Find, Fix And Learn With Cadence Online Support

We recently rolled out a new online support mechanism that replaces Sourcelink called…

• 1 min read
Sourcelink , Cadence Online Support , Digital Implementation

Analog/Custom Design

Things You Didn't Know About Virtuoso: ViVA (Part 2)

This week's installment, boys and girls, is brought to you by the letters H, V, m…

• 3 min read
ViVa-XL , IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Verification

OVM Innovation Means Business

Today, Cadence recognized it's OVM team for their innovative contribution to the…

• 2 min read
SystemVerilog , innovation , OVM ML , Functional Verification , OVM , OVM e , OVM SV , e , eRM , OVM SC , OVMWorld

Verification

Today's Innovation Awards and The "Trailblazer" Marathon

Today myself and the whole Trailblazer team are proud to celebrate the success of…

• 1 min read
innovation , Functional Verification , OVM , award , charity benefit

Digital Design

Cadence and Very Cool Stuff

One of the very cool things about my job is that I get to see all kinds of new stuff…

• 3 min read
PSO , innovation , MSV , Digital Implementation , FED

System, PCB, & Package Design 

What's Good About Innovation at Cadence? – It’s Alive and Well and Increasing!

I'm switching gears this week from my regular SPB technical product posts to focus…

• 3 min read
innovation , PCB design

Analog/Custom Design

Things You Wish You'd Thought Of...But You're Glad Someone Did!

On Tuesday this week we are celebrating "Innovation Day" here at Cadence, honoring…

• 1 min read
innovation , Custom IC Design

Verification

Emulation Is Here To Stay

A recent blog by Brian Bailey covered the emulation war. I would like to correct…

• 1 min read
System Design and Verification , Emulation

Verification

From Cadence Earning Call This Week

In system development, we have focused on two key customer challenges. First…

• 1 min read
TLM , NVIDIA , ITRI , Silicon Hive , System Design and Verification , OVM , Nethra Imaging , Rhode , Schwartz
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