System Design and Verification Blogs

The Cadence tool flow is the most comprehensive flow around. If there is an EDA need, you can rest assured that Cadence has a tool that covers that need, and you can be certain that it integrates into the rest of the flow smoothly. In fact, Cadence t...

As the de facto IO interconnect technology, PCIe has commendably addressed the performance bottleneck at the IO interface by doubling the bandwidth support every 3-4 years over the course of 5 generations of the specification and with Gen 6 at 64GT/s in the works. However, the datafication of everything requires that the raw data be processed and/or harvested for meaningful information. The high computational workloads...

Draft 1.0 of 802.3ck, also known as 100G per lane, was finally published by IEEE in Dec 2019. This draft provided the standardization of higher lane speed support for backplane systems, including 3 speed mode variations: 100G, 200G, and 400G. Backplane Ethernet speed is increasing, evolving from 10G, 25G, 50G, to current 100G on a single SerDes lane within less than 10 years, offering unprecedented capacity for the datacenter...

USB is one of the most widely used interfaces in the PC market for more than 20 years. Though it remains the same form in laptops and servers, it never stops its evolution in terms of capacity and speed. Embedded USB2.0, known as eUSB2, was created to address the concerns of power efficiency and portability. Although eUSB2 largely reuses USB2.0 protocol layer, the verification of eUSB2 can be never thought of as a miniature...

Verifying lane adapter state machine in a router design is quite an involved task and needs verification from several aspects including that for its link training functionality. The diagram below shows two lane adapters connected to each other and each going through the link training process. Each training sub-state transition is contingent on conditions for both transmission and reception of relevant ordered sets...

USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic through a hierarchy of USB4 routers. The key to tunneling of these protocols is routing table programmed at each ingress adapter. An entry of a routing table maps an incoming HopID, called Input/Ingress HopID to a corresponding pair of Output/Egress Adapter and Egress/Output HopID. The responsibility of programming routing tables lies...

A little bit of everything in the blog today: PSS is All Over As someone that was involved with UVM and PSS, both becoming Accellera standards, it is exciting to see both growing independently and together. With PSS we had a massive amount of papers ...

Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router. Put in simple terms, such tunneling involves the conversion of the respective native USB3, DP, or PCIe protocol traffic into the USB4 transport layer packets, which are tunneled...

With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions...

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...

Unlike previous years, the annual NVM Express Developer’s Conference was held in Fremont instead of San Jose. A well-attended event for the 120+ member consortium, this was a fantastic opportunity for developers to network and discuss new developments and how to keep NVMe simple, fast and scalable. Robust growth across client, enterprise and cloud segments was shown with data from Forward Insights. With a hockey stick...

In my predictions for 2018 I had identified five key trends driving verification in 2018 – Security, Safety, Application Specificity, Processor Ecosystems and System Design Enablement, all centered around ecosystems. Looking back now as the yea...

Cadence continues to be a leader in SoC verification and has expanded our industry investment in Accellera portable stimulus language standardization. Some customers have expressed reservations that portable stimulus requires the effort of learn...

In 2006, the Video Electronics Standards Association (VESA) designed a new display interface to compete with HDMI: the DisplayPort. Since then DisplayPort has become more and more popular in the computer world. Let’s take a look at the evolutio...

Consumer demand for advanced driver assistance and infotainment features are on the rise, opening up a new market for advanced Automotive systems. Automotive Ethernet allows to support more complex computing needs with the use of an Ethernet-based network for connections between in-vehicle electronic systems. The number of vehicles with automotive Ethernet began picking up over the last years, at which time BMW,...

Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and...

Cadence pulled a fast one at DAC 2018, almost like a bait and switch. We advertised a hands-on workshop to learn about Accellera Portable Stimulus Specification (PSS) v1.0. But we made participants compete head to head, for prizes, and their pride! T...

There’s nothing like the heat of a DAC demo to stress new technology and the engineers behind it! Such was the case at DAC 2018 at the new locale of Moscone Center West, San Francisco. Cadence and AMIQ were two of several vendors who announced ...

The release of PCIe 4.0 rev 1.0 in October 2017 was anticlimactic after the announcement of PCIe 5.0 rev 0.3 at last year’s PCI-SIG DevCon. Fast forward, this year’s DevCon has kicked off and the SIG is clearly demonstrating its commitmen...

We’re thrilled to have announced our prototype 7nm DDR5 IP silicon based on a preliminary version of the DDR5 standard at this week's TSMC Technology Symposium. This has been a huge amount of work from the DDR teams at Cadence and sets a landmark for the adoption of a new memory standard in the industry. This has been quite an experience for us, starting in 2017 when we developed the prototype DDR5 PHY and DDR5 Controller...

As discussed in the previous installments of the blog, the recent update of the AMBA ® 5 ACE/AXI specification introduced several performance improvement features which align the AMBA5 ACE/AXI protocol with AMBA 5 CHI (Coherent Hub Interface) specification. Among them is the new class of atomic transactions, discussed in-depth previously. Another new transaction class includes the new cache stash transactions which...

The amount of data we are generating and consuming has exploded in recent years. Social media, applications, multimedia streaming, 24-hour connectivity has us talking about Zettabytes of data in the data center that folks want to not only store, but analyze and access rapidly. SSDs were great to address mechanical inefficiencies of HDD. However, the constraints of the SCSI protocol still meant that you can only address...

CDNLive is a user conference, and verification is one of the largest categories of content with multiple tracks covering multiple days. Portable stimulus is one of the hottest new areas in verification, and continues to be popular in all venues. At l...

The Accellera Portable Stimulus Working Group met at the DVCon 2018 to move the process forward towards ratification. While we can't predict exactly when it will be ratified, the goal is now more clearly in sight! Cadence booth was busy with a lo...

The JEDEC UFS (Universal Flash Storage) started in 2011 with the v1.0 first specification version, supporting a bandwidth of 300 MB/s per lane. Since then JEDEC has been continuously releasing new UFS specification versions on top of the MIPI UniPro® and MIPI MPHY® evolving specs. UFS is now evolving to a new version of 3.0, reaching a total bandwidth of 2.4 GB/s. It seems that UFS keeps on slowly winning over eMMC in...