System Design and Verification Blogs

The rising customer expectations, intermingling fields and high performance needs can be satisfied with the system based design. An intelligent Systems Design strategy can offer a quicker route to an optimum design and helps to increase designers' productivity and analyzes efficiency by providing the ability to explore the entire design space. Cadence Intelligent System Strategy enables a system design revolution and...

Xcelium Simulator has been in the industry for years and is the leading high-performance simulation platform. As designs are getting more and more complex and verification is taking longer than ever, the need of the hour is plug-and-play apps that ar...

To stay ahead in competition in chip design real-time collaborations ensure traceability, speedy innovations at reduced the cost.

Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay of waveforms for glitch-accurate power estimation of multi-billion gate SoC designs.

Ensuring that the RTL designs correctly implement the C++ algorithmic intent in every circumstance is difficult to achieve with conventional verification. Learn more how Jasper C2RTL App helps to perform equivalence checking with 100x performance improvement

The increase in compute and data-intensive applications and the need for lower power consumption have resulted in a rapidly growing number of Arm-based devices in various market segments; this requires fast time to market (TTM) and support for off-t...

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making your breakfast. Verification is never truly complete; it is over when you run...

Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of rare bins using Xcelium Machine Learning. It is easy to use and has no learning curve for existing Xcelium customers. Xcelium Machine Learning Technology helps you discover hidden bugs when used early in your design verification cycle.

Design patterns for modeling configuration and reconfiguration in PSS (Portable Stimulus)

It is always beneficial to detect the defects early in the development phase prior to silicon bringup. Learn How Cadence Helium Virtual and Hybrid Studio helps in Pre-Silicon Bring up and HW/SW Co-Verification. The Helium Studio allows designers to build high-quality virtual and hybrid SoC models. Through the native integration of the runtime software engine of the Helium Studio with the Palladium Z2 platform and the...

Broadcom developed a code coverage signoff flow using Xcelium simulator’s constant propagation, and Jasper UNR App. So, in conclusion about this entire flow and the benefits of unreachability analysis from Jasper, the constant propagation and Jaspergold unreachability app helped Broadcom in reducing the effort of code coverage holes review and signoff to days. Broadcom was able to prioritize the area of stimulus generation...

Verifying bus performance by analyzing bandwidth and latency over time in chips is tricky. Renesas in collaboration with Cadence used a comprehensive emulation package and designed a new efficient bus performance verification scheme that helped them to witness a stellar performance with 160x speedup in actual simulation or emulation itself along with 16x speed up in bandwidth and latency calculation and extracting the...

DFT (Design for Testability) provides the much-needed support to the manufacturers to catch up with the increasing demand and pressure for mass production. It helps produce chips with flawless design and perfect quality for challenging applications. ...

This month, we join millions celebrating and recognizing the achievements of women. We truly value the women who inspire us and have made a difference in our lives. In honor of Women's History Month, we asked our SVG community to share which women h...

Cadence’s SVG team would like to feature two team members who are making a difference in technology, Tracy Fox. Sr. Product Engineer for DisplayPort, and Kevin Beauford, Sr. Principal Product Validation Engineer. Read below to hear what Black H...

With the increased complexity in SoC design and bigger teams, manually updating the specifications across all tools is very tedious. The biggest challenge is the lack of collaboration between the systems and teams. Traceability is another important a...

Design for Testability (DFT) simulation is crucial to the SOC design process: rapid turnaround time (TAT) allows for faster pattern verification for each netlist release and more iteration cycles during development, while efficient disk space and com...

We all know that a common language is the basis for every collaborative activity. This is true of natural languages and formal languages alike. In engineering, and specifically in the domain of hardware design/verification, domain languages and forma...

Three years ago, PSS (Portable Test and Stimulus) specification 1.0 was released and started to reshape the way design and verification engineers think about SoC level verification and testing. It took a noble idea of creating a single repr...

The Cadence tool flow is the most comprehensive flow around. If there is an EDA need, you can rest assured that Cadence has a tool that covers that need, and you can be certain that it integrates into the rest of the flow smoothly. In fact, Cadence t...

A little bit of everything in the blog today: PSS is All Over As someone that was involved with UVM and PSS, both becoming Accellera standards, it is exciting to see both growing independently and together. With PSS we had a massive amount of papers ...

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...

In my predictions for 2018 I had identified five key trends driving verification in 2018 – Security, Safety, Application Specificity, Processor Ecosystems and System Design Enablement, all centered around ecosystems. Looking back now as the yea...

Cadence continues to be a leader in SoC verification and has expanded our industry investment in Accellera portable stimulus language standardization. Some customers have expressed reservations that portable stimulus requires the effort of learn...

Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and...