Cadence Community

Back in the Saddle Again

By tomacadence | 23 Sep 2016

Nearly five years ago, I signed off with my last blog post in the Cadence Community. I’m delighted to return to the Cadence family and to resume my blogging activity. My former colleagues have welcomed me back warmly, and I hope that those of you who have read some of my previous posts will also be pleased to see me back. All of my posts are still online and I may reference them from time to time since many of the...

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pswg | Perspec | System Design and Verification | System simulation and analysis | Accellera | portable stimulus | System Design and Verification | verification
How to Maximize Your Verification Experience at DAC 2016

By Frank Schirrmeister | 2 Jun 2016

Next week will mark the annual EDA gathering in Austin. For me it is my 20 th DAC … I know, compared to some I am still wet behind my ears, but that’s only because I started my career in embedded software and actual chip development. I already outlined in my Blog “ The Top Five Trends In Verification To Watch For At DAC 2016 ”. The System Development Suite is all about the connection between...

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dac2016 | DAC | Verification Computing Platform | Protium | Palladium | Prtable Stimulus
Cheating Tetris

By rmathur | 24 Nov 2015

Remember Tetris? We’ve all played it at some point in our lives. You know, the game with falling blocks of different sizes and shapes where you have to place the incoming blocks in an optimal way to make full use of the available open spaces. Well, once the incoming rate of the falling blocks increases, you inevitably start to place them non-optimally and create ‘holes’ in the build. From a simple...

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Verification Computing Platform | Palladium | Tetris | Emulation
Accelerating the Next Big Shift in Verification

By Frank Schirrmeister | 8 Sep 2015

Today Cadence announced that we are aligning our proposal to the Accellera Portable Stimulus Working Group (PSWG) with the other two commercial vendors in this market – Mentor Graphics and Breker – to deliver a joint contribution, intended to accelerate the standardization process. More on this below. We at Cadence believe that portable stimulus standardization will be the hallmark of next generation verification...

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pswg | scenario | UML | software-driven verification | Accellera
Double-Take: Improving Validation Test Suite with System-Level, Coverage-Driven Verification

By rmathur | 31 Jul 2015

Application Spotlight When Freescale wanted to measure the coverage of their validation test suite for their automotive products, they determined that that the memory map coverage approach wasn’t adequate. They needed a different way to enable coverage collection. They decided to port their post-silicon code into a pre-silicon environment and use the native coverage support of the Palladium XP platform to score...

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validation test suite | Freescale | Coverage-Driven Verification | Palladium XP | verification
Use Model Versatility Is Key for Emulation Returns on Investment

By Frank Schirrmeister | 20 Jul 2015

It is always great to see when customers confirm what we in product management put forward as key elements for our product. As my team owns the product management for emulation, DAC 2015 in San Francisco was once again a great opportunity to check in with customers. And given that that imitation is the proverbial sincerest form of flattery, it was even nice to see the competition join the camp and putting more than their...

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ROI | use models | Emulation | DAC 2015 | System Design and Verification
DAC 2015 – Join Us to Experience the Continuum of Verification and System Development Engines!

By Frank Schirrmeister | 4 Jun 2015

The biggest yearly event in electronic design automation (EDA) is due to take over San Francisco next week, together, apparently, with the Apple developer community, to take over the Moscone Convention Center. This is the first DAC at which all three big EDA vendors will talk about their continuum of verification engines. I will continue to point out (until being stopped) that Cadence was the first vendor to announce...

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cadence | EDA | Moscone Center | DAC 2015 | verification | system development
Double-Take: Power Event Monitoring and In-Circuit Acceleration

By rmathur | 20 Feb 2015

For a number of years now, AMD has been applying an advanced acceleration use case referred to as hybrid verification. It’s basically a verification run utilizing the strengths of two verification engines -- in this case, a virtual platform and an emulation platform. This hybrid verification use case helps AMD achieve application-level performance well beyond traditional emulation speeds, resulting in improved debug...

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power event monitoring | Verification Computing Platform | system-level validation | hybrid verification | hardware assisted verification | Palladium XP | Emulation | in-circuit acceleration
Code Coverage at the System Level with Hardware-Assisted Verification? Are You Kidding? (Part I)

By rmathur | 9 Dec 2014

Short answer: Nope, not kidding. You can get value from applying code coverage with hardware-assisted verification by focusing on actionable data. Longer answer, keep reading below to learn more. Functional coverage is a technique to verify that a design conforms to a specification – it helps engineers examine whether a design does what it is intended to do. Code coverage provides insights into testing completeness...

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hardware-assisted verification | code coverage | functional coverage | verification closure | verification
Code Coverage at the System Level with Hardware-Assisted Verification (Part II)

By rmathur | 3 Dec 2014

In yesterday’s Part I blog post , I talked about a technique for focusing code coverage efforts on actionable data—namely, focusing on higher level connectivity. Here, let’s discuss a second technique to support system-level code coverage with hardware-assisted verification. This technique involves performing deep analysis only in particular regions of the design. Figure 1: Apply code coverage...

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hardware-assisted verification | code coverage | system-level code coverage | coverage analysis | functional coverage
Looking Back at a Great Week for System Design!

By Frank Schirrmeister | 5 Oct 2014

Reflecting on last week at ARM TechCon, together with our close partner ARM, we had a great week for System Design! You can see an overview of all our activities at TechCon 2014 here . First, on Monday, we announced the extension of our partnership to access ARM Technology to optimize our offerings for their products, both the IP as well as ARM's system development tools (like the Fast Models from ARM). Yes, another...

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debug | System Design and Verification | embedded software | hybrid | ARM TechCon 2014 | ARM | verification
Cadence Palladium Platform and ARM Fast Models - Making the Future the Present

By Frank Schirrmeister | 2 Oct 2014

In its 10 th year now, ARM TechCon is in full swing this week at the Santa Clara Convention Center. Being an engineer in a specialized field, it is sometimes difficult for me to explain to family and friends what I actually do. I have used several analogies from different perspectives in the past, as they can be seen from a mountain to house re-modeling, for which one can use abstract models. Well, courtesy of one...

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NVIDIA | Palladium | hybrid | Emulation | ARM Fast Models | ARM
The webinar on “Effective system-level coverage” does an effective coverage of the talk

By Sumeet Aggarwal | 5 Sep 2014

If you're anything like I am, you listen to webinars with one ear, occasionally checking your computer screen if a graph or image is referenced, perhaps catching up on email or articles while the webinar is running in the background. I have always struggled to know whether it is the timing of the event or boring content that has caused this. However, it is strange that I am the one who made the choice to attend at...

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system-level coverage | PXP | hardware assisted verification | webinar | Palladium XP | hardware acceleration | EDA webinar | hardware accelerated verification
Boost Efficiency and Performance of Simulation Acceleration Through New Rapid Adoption Kits

By Sumeet Aggarwal | 7 Aug 2014

The state-of-the-art Palladium XP hardware/software verification computing platform unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity. As impressive as the platform is, it is equally important for those who develop these superior solutions to provide good self-help training material, as well as tutorials to reduce the learning curve...

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ICE | sim accel | IXCOM | Palladium XP | COS Cadence Online Support | Simulation acceleration | hsv | RAKs | stb
DAC 2014—ESL Design Is Dead... Long Live ESL!

By Frank Schirrmeister | 27 May 2014

Next week the EDA industry is getting together in San Francisco for Design Automation Conference 2014. As I pointed out in a recent blog called " Confessions of an ESL-Aholic ", the scope of electronic system level (ESL) design has changed quite a bit over the last 15 years, but there is still a lot of promise, and a lot to come. The basic premise of my soberness on classic ESL is that the basic momentum upwards...

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DAC | Frank Schirrmeister | ESL
The Importance of Ecosystems in the Internet of Things Era

By Frank Schirrmeister | 10 Mar 2014

As we develop electronics in early 2014, the battle between processor architectures is raging in all spaces, from deeply embedded through mobile to servers. Choosing the right ecosystem partners is crucially important, and today's announcement of an extended partnership between ARM and Cadence marks important steps towards increasing productivity for ARM-based designs. About two years back, I had tried to make...

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ARM ecosystem | System Design and Verification | electronics design | Internet of Things | ARM | embedded systems
Recap of Another Successful Japan C-to-Silicon User Seminar

By Jack Erickson | 13 Jan 2014

Back in November, our Japan office hosted a C-to-Silicon Compiler user meeting. They host about two per year, and the meetings have been growing in size and content. The November session drew 44 customers, representing 13 companies. The content spanned about a half day, covering a wide variety of topics. The user meeting started off with a C-to-Silicon business update, presented by our Japan region marketing lead for...

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C-to-Silcon | Renesas | Japan user group | high level synthesis | Fujitsu | Casio
New Capabilities in the C-to-Silicon Compiler 2013 Releases

By Jack Erickson | 6 Jan 2014

2013 was a banner year for high-level synthesis and C-to-Silicon Compiler in particular. We saw our customers take on over 75 new projects using C-to-Silicon, much of that coming from expanded adoption within our existing customers. These designs spanned everything from algorithm-intensive designs like image processors to control-dominated designs like H.265 and high-speed cache controllers to various mixtures such as...

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13.1 | C-to-Silcon | 13.2 | pipeline functions | high level synthesis | RTL schematic
Accelerating Code Coverage Using Palladium XP Rapid Adoption Kit

By Sumeet Aggarwal | 25 Nov 2013

Code coverage is an effective tool in the verification process, giving insights into testing completeness as well as identifying highly active or inactive areas of a design. Collecting code coverage in simulation on large designs can be a very time-consuming process. Code coverage can be collected at emulation speeds in the Palladium XP system. The Accelerating Code Coverage Rapid Adoption Kit (RAK) defines which...

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IMC | System level verification and validation with Palladium XP | Rapid Adoption Kits | Palladium XP | UniCov Databases | Accelerated Code Coverage | RAKs | Accelerated Coverage | Assertions and Functional Coverage with covergroups.
High-Level Synthesis Now Spans the Datapath-Control Spectrum

By Jack Erickson | 20 Nov 2013

When we talk to prospective high-level synthesis (HLS) customers, one of the slides we show is a pie chart that breaks down the types of production designs (that we are aware of) for which customers have used C-to-Silicon Compiler. The current snapshot looks like this: Then we overlay this breakdown: The "primarily datapath" designs have varying amounts of control logic in them, the "primarily...

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antenna interface controller | controll logic | ITRI | NAND flash controller | C-to-Silcon | Freescale | System C | rtl compiler | data access controller | datapath | high level synthesis | Fujitsu Semiconductor
High-Level Synthesis—What Expertise Is Needed for Micro-Architecture Tradeoffs?

By Jack Erickson | 13 Nov 2013

My most recent blog post mentioned how utilizing new algorithms together with high-level synthesis can continue to drive innovation in hardware design by balancing power consumption with performance improvements. A great example of this is what Fujitsu Semiconductor was able to accomplish —they took advantage of the high abstraction level of SystemC to explore different micro-architecture tradeoffs. They...

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RAM | micro-architecture | hardware | C-to-Silcon | C | SystemC | HLS | C++
Accelerated Code and Functional Coverage Using Palladium XP

By Sumeet Aggarwal | 10 Nov 2013

Code coverage is an effective tool in the verification process—giving insights into testing completeness as well as identifying highly active or inactive areas of a design. Collecting code coverage in simulation on large designs can be a very time consuming process. Now, code coverage can be collected at emulation speeds in the Palladium XP system. Eric Melancon, HSV Staff PE, explains through his first...

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IMC | Cadence Online Support | UXE | Palladium XP | Incisive Verification Environment | support.cadence.com | Accelerated SV Covergrooups | Accelerated Coverage | IES
Starting Virtual Platform Simulation with Cadence Software Developer

By jasona | 11 Oct 2013

Last time, I provided an introduction to the Eclipse setup for the Cadence Virtual System Platform . This time I will explain how to run simulation using Software Developer. Cadence Software Developer provides multiple flows to hand off virtual platform simulations to software engineers. The easiest flow can be used when the platform creator and software developer are working at the same company and on the same network...

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eclipse | Virtual System Platform | Embedded Software Debugging | Incisive
Combining the Linux Device Tree and Kernel Image for ARM

By jasona | 8 Oct 2013

Back in 2010, I wrote two articles about a SystemC model used to load the Linux kernel and its various artifacts into memory for ARM virtual platforms. The first was A SystemC TLM 2.0 ARM Linux Boot Loader and the second was More on the SystemC ARM Linux Boot Loader . At the time I covered the kernel, Linux kernel command line, and RAM-based file system. Not too long after those articles most ARM systems started using...

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Virtual System Platform | virtual platforms | TLM | ARM kernel image | virtual prototypes | VSP | zimage | boot loader | System Design & Verification | SystemC | Linux device tree | ARM | system-level | linux | Jason Andrews | ESL | kernel
Getting Started with the Cadence Virtual System Platform: Software Developer

By jasona | 8 Oct 2013

Cadence Software Developer is an exciting Eclipse-based product for developing, debugging, and analyzing embedded software. It has a long list of powerful capabilities that will make your job a lot easier - including transparent and intuitive one-click launch of the virtual platform simulator, multi-core, multi-process, multi-OS embedded software debug, hardware-aware software debug, and analysis via a programmer's...

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eclipse | Virtual System Platform

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