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Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 3 of 3)

By Steven Brown | 16 Oct 2017

Here we conclude the blog series and highlight the results of Mediatek 's use of Cadence Perspec™ System Verifier for their SoC level verification. In case you missed it, Part 1 of the blog is here , and Part 2 of the blog is here . One of their key objectives was increasing productivity producing mixed directed-random tests. Here in Figure 9 you can see how Mediatek has ordered a series of actions in a directed...

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uvm | Perspec | coherent | perspec system verifier | coherency library | coherency | Accellera | mediatek | ARM | pss | portable stimulus
Celebrating Five Years of Performance-Optimized Arm-Based SoCs: Now including AMBA5

By Steven Brown | 12 Oct 2017

It’s been quite a long 5-year journey building and deploying Performance Analysis, Verification, and Debug capabilities for Arm-based SoCs. We worked with some of the smartest engineers on the planet. First with the engineers at Arm, with whom we collaborated to develop and validate our solutions with their IP. Then with the top customers in the world, who must continually overcome increasing SoC complexity due...

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iwb | interconnect | amba5 | Interconnect Workbench | Palladium | Performance Analysis | AMBA | CoreLink | xcelium | ARM
When Arm meets Intel – Overcoming the Challenges of Merging Architectures on an SoC to Enable Machine Learning

By Steven Brown | 29 Sep 2017

As the stakes for winning server segment market share grow ever higher an increasing number of companies are seeking to grasp the latest Holy Grail of multi-chip coherence. The approach promises to better enable applications such as machine learning, network processing, in-memory data base, and other large dataset tasks. Arm and its partners continue to pursue the server market long dominated by Intel. The results will...

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SoC verification | perspec system verifier | Accellera | pss | portable stimulus
Making it Easier to Apply Palladium Z1 to SoC Performance Analysis

By XTeam | 23 Sep 2017

Recently, Renesas combined the Cadence® Interconnect Workbench, the Cadence vManager™ Metric-Driven Signoff Platform, and the Cadence Palladium® Z1 Enterprise Emulation Platform to improve their performance validation flow. They were looking for a better way to analyze their performance results so trade-off decisions could be made faster—a task well suited to Interconnect Workbench. Each new generation...

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Interconnect Workbench | customer feedback | success story | Palladium | Renesas
How to Get to a Trillion Devices in the Internet of Things in 2035

By Frank Schirrmeister | 12 Sep 2017

Next month at Arm TechCon, one of the key discussion topics with be the internet of things (IoT), especially after Masayoshi Son, Arm's "parent" Softbank’s CEO, took the stage last year and boldly predicted that “more important, in the next 20 years, we will see 1 trillion internet of things devices.” So that means 1 trillion devices in 2035. That’s not too far in the future! Are...

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prototyping | cadence | palladium z1 | IoT | Socrates | Emulation | Internet of Things | ARM | protium s1 | verification
How To Create L3 Cache Command Overflow Stress Test in Less Than 2 Days

By Steven Brown | 5 Sep 2017

One category of difficult SoC tests to create are stress tests, to validate the limits of SoC functionality and its behavior in this scenario. It’s usually not overloading a data input port that is challenging; something that can be accomplished with singular focus. The elusive stress tests are those that create conditions wherein a system resource becomes overwhelmed by requests from the myriad initiators that...

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SoC verification | perspec system verifier | Accellera | pss | portable stimulus
Do You Have The Tools You Need To Verify Your ARM Multi-core, Coherent SoC?

By Steven Brown | 21 Aug 2017

Multi-core, coherent SoCs are very complex and verifying their behavior requires a system level perspective that is not easily acquired. As more devices incorporate the coherent multi-core architecture out of competitive necessity, organizations are grappling with the challenges of achieving high quality. This presents a unique opportunity for Cadence to provide libraries for use with the Cadence Perspec System Verifier...

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SoC verification | perspec system verifier | Accellera | ARM | pss | portable stimulus
How to Model State Machines in the Accellera Portable Stimulus Standard for Low Power SoC Verification

By Steven Brown | 4 Aug 2017

The Accellera Portable Stimulus Standard (PSS) is experiencing growing customer interest, and generating a host of questions. In this blog Sharon Rosenberg details the modeling of state machines using the PSS in order to perform low power SoC verification, followed by a demonstration of the same in Perspec. In addition he clarifies the term “Graph” as it is used in relation to the PSS. (Please visit the...

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Low Power | SoC verification | perspec system verifier | Accellera | pss | portable stimulus
Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 2 of 3)

By Steven Brown | 13 Jul 2017

Here we go through the application of Cadence Perspec™ System Verifier by Mediatek for their SoC level verification. In case you missed it, Part 1 of 3 can be found here . As shown in Figure 5 , the tests are generated automatically from the model and a corresponding scenario. Each test is automatically adapted to the target verification engine, whether a virtual platform like the Virtual System Platform ...

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uvm | Perspec | coherent | perspec system verifier | coherency library | coherency | Accellera | mediatek | ARM | pss | portable stimulus
Mediatek Deploys Perspec for SoC Verification of Low Power Management

By Steven Brown | 12 Jul 2017

Mediatek has been using the Cadence Perspec™ System Verifier for their SoC level verification. At a recent CDNLive , Mediatek reported on their experience with Perspec and the results from their first phase of deployment. Their primary goal in adopting Perspec is to improve verification efficiency for their line of complex mobile application processor SoCs, each employing an ARM-based multi-core, cache-coherent...

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uvm | Perspec | coherent | perspec system verifier | coherency library | coherency | Accellera | mediatek | ARM | pss | portable stimulus
See Perspec Running Accellera Portable Stimulus Examples Here and Now!

By Steven Brown | 15 Jun 2017

Accellera has announced the release of an Early Adopter specification of the Portable Stimulus Standard (PSS) for public review. First introduced in detail at DVCON 2017, it will be the subject of a tutorial at DAC 2017 . We receive many questions about the PSS, and here we provide some detailed information about the standard, and setup for a demonstration of Cadence Perspec System Verifier using the new standard as...

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SoC verification | perspec system verifier | Accellera | pss | portable stimulus
Accellera Has Done It Again! Portable Stimulus Standard Available For Review

By Steven Brown | 15 Jun 2017

In a press release this morning, Accellera announced availability of an Early Adopter specification of the Portable Stimulus Standard (PSS) for public review, just in time for DAC 2017 in Austin! Public review of the PSS specification will end September 15 th , so your summer reading plans are now set! We are pleased with this standard release and believe that it has the potential to provide a huge leap in automation...

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CDNS | Perspec | Accellera | pss | portable stimulus
Have You Fully Verified Your Multi-Core, Cache-Coherent SoC? Find Out How we Can Help @ DAC!

By Steven Brown | 24 May 2017

You might have thought it would be “just another DAC” this year, again in Austin, where the food and live entertainment is undeniably superb. But wait, there’s help for improving verification of your cache coherent multi-core SoC, one of the biggest challenges for today’s mobile and server verification teams. This year’s DAC holds several opportunities to learn how to make improvements, and...

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DAC | SoC verification | Perspec | pss | Accellera PSS
SoC Verification with Portable Stimulus Using Perspec System Verifier

By Steven Brown | 23 Apr 2017

This year’s CDNLive San Jose was another gem. Many great keynotes, customer presentations, and technical updates. There were several mentions of Machine Learning, both in general about the emergence of Artificial Intelligence in the world, and specifically on its application to EDA challenges. And there was a lot of focus on speed—the world’s first production proven parallel simulator, Xcelium , along...

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SoC verification | Perspec | perspec system verifier | Qualcomm | portable stimulus
A Seamless Path to the Portable Stimulus Standard

By tomacadence | 23 Mar 2017

In our last blog post , we reviewed some of the activities at the recent Design and Verification Conference and Exhibition ( DVCon ) in San Jose. Portable stimulus was clearly one of the hot topics at the event, with a tightly packed room for the "Creating Portable Stimulus Models with the Upcoming Accellera Standard" tutorial , featuring members of the Accellera Portable Stimulus Working Group ( PSWG ). ...

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uvm | prototyping | pswg | Acceleration | Functional Verification | Perspec | System Design and Verification | Palladium | SoC | Emulation | Simulation acceleration | DVcon | Accellera | metric-driven verification | Hardware/software co-verification | portable stimulus | simulation | verification
Portable Stimulus Shines at DVCon

By tomacadence | 4 Mar 2017

For me, this week was almost entirely consumed with the Design and Verification Conference and Exhibition ( DVCon ) at the familiar DoubleTree in San Jose. The hotel has replaced its chandeliers with shiny new space-age fixtures, but otherwise, I felt at home with the usual strong technical program and many chances to network with customers and colleagues. Following up on my preview post a few weeks ago, I will provide...

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uvm | prototyping | pswg | Acceleration | Functional Verification | Perspec | System Design and Verification | Palladium | SoC | Emulation | Simulation acceleration | DVcon | Accellera | metric-driven verification | Hardware/software co-verification | portable stimulus | simulation | verification
What Sort of Bugs Does Portable Stimulus Find?

By tomacadence | 17 Feb 2017

In a recent blog post , we discussed some general concepts of bugs, problems, issues, and features. We gave examples of different types of bugs typically found during the functional verification of chip designs, and made the claim that “portable stimulus and software-driven verification are excellent at finding all the categories of functional bugs.” In today’s post we’ll back up this claim by...

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hardware-software co-verification | uvm | Low Power | pswg | debug | Functional Verification | System Design and Verification | embedded software | Emulation | Accellera | Hardware/software co-verification | debugging | portable stimulus | interrupts
Preview of an Exciting DVCon

By tomacadence | 2 Feb 2017

In the overall world of EDA, the Design Automation Conference ( DAC ) is the biggest annual event for the industry. Nothing against DAC, but if you’re involved in functional verification as I am, the Design and Verification Conference and Exhibition ( DVCon ) in San Jose is more focused and arguably more important. Most people think of this as primarily a verification venue, but if you note the “and”...

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uvm | prototyping | pswg | Acceleration | Functional Verification | Perspec | System Design and Verification | Palladium | SoC | Emulation | Simulation acceleration | DVcon | Accellera | metric-driven verification | Hardware/software co-verification | portable stimulus | simulation | verification
Bare Metal Tests and Hardware-Software Co-Verification

By tomacadence | 23 Jan 2017

One interesting question that arises from time to time is whether the Cadence® Perspec ™ System Verifier can verify software as well as hardware. The question is simple enough, but the answer is more complex. There are at least two versions of “yes”, although the most common usage of the tool is focused almost entirely on verifying an RTL design. This post attempts to explain all this, and in doing...

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hardware-software co-verification | uvm | pswg | Acceleration | Perspec | virtual platform | System Design and Verification | Emulation | System simulation and analysis | Accellera | FPGA prototypes | testbench | portable stimulus | silicon | bare metal | verification
Bugs, Problems, Issues, and Features

By tomacadence | 4 Jan 2017

There’s no better way to demonstrate the value of a verification tool than to find a killer bug in the customer’s design. When the verification engineer looks up from the screen and says, “Wow – we might never have found that!” we EDA vendors are equally happy. Finding a bug is a great way to conclude a technical evaluation with a prospective customer or drive wider usage of a tool at a current...

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performance | uvm | pswg | Functional Verification | Perspec | OVM | issue | bug | feature | Accellera | Problem | portable stimulus
Report From the 17th MTV Workshop in Austin

By tomacadence | 20 Dec 2016

Austin is always a nice place to visit, and last week I spent a few days there to attend the 17th International Workshop on Microprocessor and SOC Test and Verification ( MTV ). The event is held on the top floor of the Hyatt Regency Hotel, with spectacular views of the ever-growing Austin skyline. Some predict that within ten years it will replace San Jose as the tenth-largest city in the country. It seems possible given...

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security | Perspec | Safety | formal | workshop | SoC | Test | ISO 26262 | MTV | power | microprocessor | portable stimulus | verification
Perspectives on Developing EDA Standards

By tomacadence | 6 Dec 2016

Last week, my colleague Paul McLellan published a blog post on the standardization work underway within the Portable Stimulus Working Group ( PSWG ) of Accellera Systems Initiative. He did a nice job of describing portable stimulus as the PSWG defines it and showing the broad scope of users and verification platforms that the standard proposes to address. It should be clear that this is far from a simple problem and no...

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uvm | 1394 | pswg | Perspec | OVM | USB | IEEE 1500 | Accellera | VCX | VCi | PCI | portable stimulus
A Personal History of Functional Verification

By tomacadence | 18 Nov 2016

In my most recent blog post , I summarized some of the key points from an October presentation at DVClub Silicon Valley by Dave Brownell from Analog Devices. As part of his introductory section on the motivation for the industry to move to portable stimulus, Dave summarized the history of design verification into six phases: Verification? – little or no verification Directed Testing – minimal hand...

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ASIC | uvm | pswg | formal. Verisity | Functional Verification | System Design and Verification | OVM | System Development Suite | constrained-random | Simulation acceleration | Accellera | metric-driven verification | Virtual Platforms | Hardware/software co-verification | simulation | FPGA | System Design and Verification
Analog Devices Promotes Portable Stimulus at DVClub

By tomacadence | 3 Nov 2016

If you’re not familiar with the series of DVClub events held in North American, Europe, and Asia, please consult my most recent blog post for a brief history. These events offer a unique opportunity for hands-on verification engineers to network with their peers, hear from one of their own about an interesting recent project or a new verification technology, and chat informally with the sponsoring vendors about...

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Analog Devices. ADI | pswg | cadence | debug | System Design and Verification | Dave Brownell | software | Accellera | System Design & Verification | portable stimulus | System Design and Verification | verification
DVCon(x2), DVClub(x2): Portable Stimulus Is Everywhere

By tomacadence | 21 Oct 2016

In my most recent blog post , I talked about the industry vision for portable stimulus as a way to improve verification reuse, automate test creation, and enhance coverage. The Accellera Portable Stimulus Working Group (PSWG) is working hard on a standard to define the reusable input models for the test generation process. As Secretary of the PSWG, I have a front-row seat as this important new verification technology...

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horizontal reuse | DAC | uvm | prototyping | pswg | Perspec | System Development Suite | DVClub | Emulation | DVcon | Accellera | portable stimulus | simulation | System Design and Verification

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