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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

What's New in PSS 3.0? Key Additions to the Portable Stimulus Standard

The Portable Stimulus Standard (PSS) Language Reference Manual (LRM) has evolved…

• 6 min read
SoC verification , Perspec , SoC , pss

Smarter Chips, Faster Checks: GravityXR Leading the XR Verification Shift

As XR technology accelerates, complexity rises—but speed to market remains the ultimate…

• 2 min read
performance , AVIP , GravityXR , virtual platforms , cadence , debug , Palladium , hybrid , Emulation , XR , testbench , verification

VESA Adaptive-Sync V2 Operation in DisplayPort VIP

Need for Synchronization In a computer system, both the GPU as well as the monitor…

• 5 min read
Target Refresh Rate , Screen Tearing , VSync , GPU , Adaptive Sync , FAVT , Adaptive Sync SDP , display , VIP , DisplayPort , Gaming Content , GSync , Cadence VIP , FPS , Monitor , Video Content , Vertical Expansion/Reduction , VESA , AVT , Screen Stuttering , Frame Rate , VTotal , Video Frame , DisplayPort VIP , VRR , frame , Refresh Rate , FreeSync

ONFI 5.2: What’s new in Open NAND Flash Interface's latest 5.2 standard

Non-volatile memories like Nand Flash are key components of most modern system-on…

• 3 min read
Verification IP , non-volatile memory , flash , ONFT5.2 Vs ONFI5.1 , ONFI , VIP , memory models , ONFI5.2 , NAND , sca

Powering Up Efficiency: A Deep Dive into CXL L0p and its Verification

Compute Express Link (CXL) is revolutionizing data center architecture, with power…

• 3 min read
CXL , performance , Verification IP , Functional Verification , coherent , l0p

Demystifying CXL Memory Interleaving and HDM Decoder Configuration

Memory interleaving is a technique that distributes memory addresses across multiple…

• 5 min read
CXL , Verification IP , VIP , PCIe

Demystifying Forward Error Correction (FEC) in PCIe 6.0

Introduction As the industry continues to progress in PCIe, enabling faster and…

• 3 min read
Verification IP , PCIe 6.0 , PCI Express , verification , TripleCheck

Don’t Let Constraint Random Verification Become Your Nightmare!

Use a graphical view to help with debugging by harnessing visual tools to demystify…

• 6 min read
SystemVerilog , uvm , debug , Functional Verification , random , Verisium Debug , constraint , verification

PCIe Low-Power Validation Challenges and Potential Solutions (PIPE/L1 Substates)

As chip complexities increase and the industry evolved to more battery-powered devices…

• 3 min read
Verification IP , Low Power , PCIe , verification

Regressions, Coverage Integration, and Verification Closure

Don't miss this opportunity to streamline your verification flow and achieve faster…

• 1 min read
webinar , verification

Streamlining Digital Front-End Design and Verification with Cadence Tools

Plan, Simulate, and Debug: Streamlining Digital Front-End Design and Verification…

• 1 min read
webinar , xcelium , verification

Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained

Introduction The Flit Sequence Number is a mechanism introduced in the PCIe 6.0…

• 5 min read
Verification IP , VIP , Flit Sequence Number , PCIe , PCIe 6.0 , flit mode , verification

Evolution of AMBA AXI Protocol: An Introduction to the Issue L Update

To gain a comprehensive understanding of AMBA® AXI Issue L (AXI-L) protocol update…

• 3 min read
AXI , Verification IP

An Introduction to AMBA CHI Chip-to-Chip (C2C) Protocol

As chip designs grow larger and more complex, they become increasingly difficult…

• 2 min read
C2C , multi-die , chip-chip , AMBA , CHI VIP , verification

High-Bandwidth Memory Evolution from First-Generation HBM to the Latest HBM4

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become…

• 3 min read
Verification IP , VIP , JEDEC , HBM , hbm4 , DRAM , High Bandwidth Memory , memory models , HBM3 Vs HBM4 , verification

Verification of PCIe's TDISP for Device Interface Security

The TEE Device Interface Security Protocol (TDISP) is a critical component in ensuring…

• 5 min read
Verification IP , Functional Verification , CXL3.0 , PCIe , TDISP , IDE , verification

An Overview of CXL Mode Alternate Protocol Negotiation

The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful…

• 4 min read
CXL , Verification IP , VIP , PCIe , verification

Evolution of CXL PBR Switch in the CXL Fabric

Compute Express Link (CXL) is a transformative technology that significantly improves…

• 5 min read
Fabric manager , Routing , switch , CXL3.0 , CXL switch , TYPE , SPID , PBR , DPID

UEC-CBFC: Credit-Based Flow Control for Next-Gen Ethernet in AI and HPC

For ages, Ethernet has been the backbone of networking — starting from simple web…

• 2 min read
Verification IP , artificial intelligence , Ethernet VIP , Functional Verification , VIP , UEC , machine learning , Ethernet , Hyperscalers

Training Insight: Unlocking the Power of the Xcelium Logic Simulator

In the fast-paced world of digital design and verification, simulation tools are…

• 1 min read
Xcelium Logic Simulator , Training Insights

Fast Emulation Requires Fast Debug! This Is How It is Done

Introduction Emulation has become a critical tool for verifying complex system-on…

• 3 min read
debug , Palladium , verisium , Emulation , Verisium Debug

Scalable I/O Virtualization: A Deep Dive into PCIe’s Next Gen Virtualization

The demands of modern cloud computing—massive scale, constant agility, and tight…

• 6 min read
Verification IP , Functional Verification , VIP , PCIe

LPDDR6: The Next-Generation LPDDR Device Standard and How It Differs from LPDDR5

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor…

• 4 min read
Verification IP , LOW POWER DRAM , JEDEC , LPDDR6 Vs LPDDR5 , DRAM , lpddr5 , lpddr5x , memory models , Lpddr6

UEC-LLR: The Future of Loss Recovery in Ethernet for AI and HPC

As Artificial Intelligence (AI) and High-Performance Computing (HPC) systems become…

• 2 min read
Verification IP , artificial intelligence , uvm , LLR , Functional Verification , UEC , Ethernet , HPC , Ethernet UEC , AI/ML

MIPI MPHY 6.0: Enabling Next-Generation UFS Performance

High-speed chip-to-chip data transfer is continuously evolving to meet increasing…

• 1 min read
Verification IP , UniPro , MIPI Alliance , VIP , MIPI , MPHY

Celebrating LPDDR6 Specification Publication: Cadence Hosts JEDEC LPDDR Meeting

Low-power DDR SDRAM is one of the most widely used memories in the semiconductor…

• 2 min read
Verification IP , Design IP , JEDEC , LPDDR PHY IP , DRAM , lpddr5 , LPDDR Controller IP , memory models , Lpddr6

Training Webinar on Protium X3: Using FullVision for Debugging

Join me, Sandeep Nasa, Senior Principal Education Application Engineer, in our free…

• 1 min read

The Evolution of CXL.CacheMem IDE: Insights into CXL3.0 Security Feature

In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe…

• 3 min read
CXL3.0 , VIP , PCIe , verification
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