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Digital Design: Understanding Clock Gating Report and Cells

MJ Cad

Hi everyone, Are you interested in reducing the power dissipation of your design? Who wouldn’t? What about taking the advantage of Clock Gating? Clock Gating is a technique that enables inactive clocked elements to have gating logic automatical...
- 19 Feb 2021
System, PCB, & Package Design : Sigrity and Systems Analysis 2021.1 Release Now Available

SigrityReleaseTeam

The Sigrity and Systems Analysis 2021.1 release is now available for download at Cadence Downloads. For the list of CCRs fixed in the 2021.1 release, see the README.txt file in the installation hierarchy. SIGRITY/SYSANLS 2021.1 Here is a lis...
- 19 Feb 2021
カスタムIC／ミックスシグナル: Spectre Tech Tips: Spectre X RF解析の使用

Custom IC Japan

2020年9月末にSPECTRE 20.1ベース・リリースにてSpectre® X-RFがリリースされました。Spectre X-RFテクノロジはSpectreのRF解析にSpectre Xエンジンを統合します。このブログでは、Spectre X-RFテクノロジを紹介します。 Spectre X-RFの概要 Spectre X-RFは、複雑なFinFET (およびその他の) デバイス・モデルを使用した先端ノード・デザインや、多数のRCを含む大規模なポスト・レイアウト・デザインな...
- 18 Feb 2021
RF /マイクロ波設計: Cadence AWR Design EnvironmentのE-ニュースレター(2021年1月)

RF Design Japan

　日本語翻訳版をお届けします。ぜひ最新の製品に関する最新の情報をご確認ください。このニュースレターの英語版はこちらです。 Cadence AWR Design Environment E-ニュースレターの購読はこちらからご登録下さい。 All Things RF: January 2021 Cadence AWR ソフトウェアプラットフォームご登録下さい:Cadenceのシステム解析ニュースレター! 高密度のRF /ミックスドシグナル配線と部品を含む今日の無線...
- 18 Feb 2021
System, PCB, & Package Design : BoardSurfers: Training Insights: How to Assess Electrical Performance of Packages

Niharika1

In this blog, you will be taking an IC package design from Allegro® Package Designer Plus (APD Plus) and export the design to Sigrity XtractIM. You will use XtractIM to extract models from the exported package and to assess the electrical pe...
- 17 Feb 2021
Analog/Custom Design: Start Your Engines: Automatic Configuration Creation for a Mixed-Signal Test Bench

Andre Baguenie

In this post, I will cover how you can easily create an automatic configuration for a mixed-signal test bench.
- 16 Feb 2021
Verification: HyperRam as DRAM for Some Applications!!!

Chetans

Applications like Automotive, Industrial control panels, Smart Home, Smart watches, smart speakers and bends require Low cost, Low power consumption, High computing efficiency, Easy to control and Low form factor memory devices to process data temporarily to gain widespread adoption in the market place. HyperRam memory has all above characteristics to improve performance of end devices.

The HyperRam device is the high…
- 16 Feb 2021
Verification: Training Insights - Clean RTL Faster Without Simulation! Here’s How.

Nizar Hanna

RTL designers are challenged by increasingly complex designs. They’re also expected to deliver higher quality RTL to verification teams under tight schedules. And teams want to expose bugs as soon as possible—to reduce the cost per bug—which puts additional pressure on designers.

Conventional methods of design bring-up using unit-level testbenches are no longer the optimal way to address these challenges…
- 12 Feb 2021
Breakfast Bytes: Offtopic: All the Days

Paul McLellan

It's a weird confluence of days this weekend. It is the Chinese New Year on the 12th, today. It is Valentine's Day on the 14th. And it is Presidents' Day on the 15th. Cadence is off for that last one (in the US), and, as is traditional the day before...
- 12 Feb 2021
カスタムIC／ミックスシグナル: Virtuoso Video Diary: Split Symbolsとは

Custom IC Japan

何百ものピンを持つ大きな symbol は管理するのが難しく、デザインを乱雑にします。より複雑なデザインと高度なテクノロジーにおいてブロックを分割することは、どのようなデザインでも便利な機能になっています。 Split Symbols 機能は ICADVM 20.1 base リリースの Virtuoso Schematic Editor で導入され、大きな symbol を複数の部分的な symbol に分割することにより、簡単かつ効率的に管理するソリューションを提供します。&nbs...
- 11 Feb 2021
Analog/Custom Design: Virtuoso Video Diary: Performance Diagnostic Tool – An MRI Scanner for Virtuoso

Sucharita

You can now use the Performance Diagnostic tool in the Virtuoso custom IC design platform to diagnose issues that might be causing your system to slowdown or freeze. Click here to know more.
- 11 Feb 2021
Academic Network: BarCamp? 2021 DATE BarCamp!

Anton Klotz

The following text was written by Georg Gläser, one of the organizers of the edaBarCamp.de events, who also was co-organizer of the BarCamp @ DATE event. Thank you, Georg, for all your help and for this text. The BarCamp was an interactive open...
- 11 Feb 2021
Life at Cadence: An Amazing Season to Give

TramN

Giving has always been a special part of our culture at Cadence. It’s one of the reasons why I truly love working here. Our employees are so passionate about giving back to the communities where they live and work. Each year, Cadence employees ...
- 11 Feb 2021
Breakfast Bytes: DATE: Making Fabs Smarter

Paul McLellan

One of the keynotes at the recent DATE 2021 was local. Or would have been local if DATE had taken place in Grenoble as originally planned. Of course, DATE was virtual and you could watch from anywhere in the world. About the only thing truly European...
- 11 Feb 2021
Breakfast Bytes: Kneron's Experience Reducing Edge AI Processor Development Schedules with Tensilica DSPs

Paul McLellan

As late as 2010, the received wisdom among computer scientists was that neural networks would not amount to much. Those ideas had been tried repeatedly for decades and never produced practical results. Yes, our brains work that way, but it seemed tha...
- 10 Feb 2021
System, PCB, & Package Design : IC Packagers: A New Way to Create Structures

Tyler

Let’s focus today on an established routing technology with a new twist! All of you are doubtless familiar with the concept of structures – formerly called via structures, renamed to structures because of their growing flexibility and application across many flows.
- 9 Feb 2021
Digital Design: Voltus Voice: Power-Saving Chip Design Is Not a Choice; It’s a Necessity

Ramesh Sharma

A blog on how the Voltus power-gating analysis solution enables engineers to address the low-power design challenge of extending battery life while reducing the leakage power.
- 9 Feb 2021
System, PCB, & Package Design : BoardSurfers: How to Detect and Resolve Copper Void Slivers

Boopathy J

Markets today are being driven by miniaturization. As the size is decreasing, PCB designs are getting more and more complex. Manufacturing boards while also addressing the signal integrity issues is becoming a challenge. With continuous shrinkage in the pin ...
- 9 Feb 2021
Breakfast Bytes: DATE: What Is Single Pilot Operation? Airbus Q&A

Paul McLellan

Yesterday's post DATE: What Is Single Pilot Operation? Airbus Explains was the first of two about the Airbus keynote at DATE. After a pre-recorded presentation there was a live Q&A. The questions covered a lot of ground and I thought it ...
- 9 Feb 2021
The India Circuit: Tanaya Bapat: A Story of Perseverance and Strength

Asim Khan

Subsequent to my previous blog about the Cadence Scholarship Program, I bring to you another inspiring story featuring one of our students - Tanaya Bapat. The Cadence Scholarship Program At Cadence, giving back to society is of the important asp...
- 8 Feb 2021
Breakfast Bytes: DATE: What Is Single Pilot Operation? Airbus Explains

Paul McLellan

The final keynote at this year's DATE was by Pascal Traverse of Airbus, titled Autonomy: One Step Beyond on Commercial Aviation. This was part of this year's DATE's two-day special initiative on Autonomous System Design (ASD)...not t...
- 8 Feb 2021
Breakfast Bytes: Sunday Brunch Video for 7th February 2021

Paul McLellan

https://youtu.be/WUEvcW8Isxc Made on my balcony (camera Carey Guo) Monday: It's Mars Month Tuesday: SEMI Industry Strategy Symposium: The Outlook Wednesday: SEMI Industry Strategy Symposium: The Technology Thursday: A History of Semicon...
- 7 Feb 2021
Digital Design: Library Characterization Tidbits: Recovering from Failures in the Multi-PVT Characterization Flow

Rajni

Ever wondered what should you do if any arc, cell, or PVTs failed in a characterization run? Do you need to rerun the entire characterization process? Certainly not if you know about how to use the recovery workflow in the multi-PVT characterization flow! Read more...
- 5 Feb 2021
Breakfast Bytes: A History of the Mouse

Paul McLellan

I was idly watching YouTube over the break when "the algorithm" recommended that I watch a Computerphile video called How the Mouse Works. In some ways, it is a history of the computer mouse. But the history of the mouse goes back a lot fur...
- 5 Feb 2021
定制IC芯片设计 : Virtuoso Video Diary: “Training bytes” 助推知识传播—第3部分

Parula

摘要：当今，在单个设计中使用多种测试平台比以往任何时候都更为重要。因此在接下来的博客中，我们将介绍与Virtuoso ADE Product Suite 相关的使用技巧及提示，涵盖Virtuoso ADE Explorer, Virtuoso ADE Assembler 和Virtuoso ADE Verifier 等.
- 5 Feb 2021

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