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The India Circuit: Mousumi Ghorai: A Story of Courage and Confidence

Madhavi Rao

Following on from my last blog about the Cadence Scholarship Program, here is the second inspiring story featuring one of our students - Mousumi Ghorai. The Cadence Scholarship Program A few words about the Cadence Scholarship Program, in case you mi...
- 14 Oct 2020
Breakfast Bytes: Electromagnetic Compliance: Anechoic Chamber Not Required

Paul McLellan

Yesterday, I reported on Paul Cunningham's announcement of a new product, System VIP, in my post System VIP: Logistics for Cache-Coherent Systems. A few minutes later Paul announced a second product, the Clarity 3D Transient Solver. This is the...
- 14 Oct 2020
Life at Cadence: 10 Things that Make a Terrific Manager

Jaswinder

It is often said that employees join companies but leave managers. If you think back on your own career, you will likely see the truth in this statement. We all know what a bad manager looks like, but what about an extraordinary manager? The truth i...
- 13 Oct 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Quick Start for Virtuoso RF Solution

Claudia Roesch

The shift to heterogeneous integration of module designs implies a transition from PCB-styled flows and methodologies towards IC-styled flows. Cross-fabric design and verification methodologies for multi-die packages have become indispensable parts of any advanced module design flow. Cadence is uniquely positioned to lead and spearhead this transition. To address the challenges of a rapidly increasing market driven by…
- 13 Oct 2020
System, PCB, & Package Design : IC Packagers: Accurate Masking of Your Substrate Layers

Tyler

Soldermask and its brethren are stable in the EDA design industry. These layers control what is exposed to the elements (and to electrical connections!) on the top and bottom layers of the substrate. But, for many years, they have been a part of the ...
- 13 Oct 2020
Breakfast Bytes: System VIP: Logistics for Cache-Coherent Multiprocessor Systems

Paul McLellan

Today, at CadenceLIVE Europe, Paul Cunningham, the GM of the verification business unit, announced System VIP. This is another product that broadly falls under the heading of computational logistics. I think of it as logistics for cache-coherent syst...
- 13 Oct 2020
定制IC芯片设计 : Virtuoso Meets Maxwell: 裸片版图导出（Die Export）功能改头换面

deeptig

大家好! 今天，我想给大家介绍Virtuoso RF解决方案中裸片版图导出（Die Export）的最新改进功能，其中大多数功能都已在ICADVM18.1 ISR10中发布。导出的裸片的abstract包含了裸片的尺寸和边界信息以及I/O的位置信息，它作为中间文件可用于Cadence 不同工具间的信息转换（如 Innovus, Virtuoso 和Allegro ），这并不算是一个新功能，它在Virtuoso RF解决方案发布前就已经出现了。尽管如此，我们在刚开发Virtuoso RF解决方案时，仍然打算从头开始重写这个功能，这是因为它可能已过时，需要增强其性能和容量、改进其使用方式以满足现在产品需求。我们在很多阶段都做了相应的调整，最终版已在ICADVM18.1 ISR10 中完成并发布。
- 12 Oct 2020
Analog/Custom Design: Virtuosity: Verification in Virtuoso ADE Verifier - The Reliability Way!

Harsh Gupta

Starting from the IC6.1.8/ICADVM18.1 ISR12 releases, Virtuoso ADE Verifier supports Reliability in verification plans. Dive in to know more...
- 12 Oct 2020
Breakfast Bytes: Arm and NVIDIA: Simon Segars and Jensen Huang

Paul McLellan

What used to be face-to-face Arm TechCon has turned into a virtual conference under the name Arm DevSummit. In the unlikely event that you missed the news, NVIDIA announced on September 13 that it intends to acquire (most of) Arm for $32B from ...
- 12 Oct 2020
Breakfast Bytes: Sunday Brunch Video for 11th October 2020

Paul McLellan

https://youtu.be/0oRah8lCf4M Made in front of my TV Monday: Jasper User Group 2020 Preview Tuesday: Innovus Mixed Placer Wednesday: TSMC OIP: Rent's Rule and Fast SerDes IP Thursday: Bessemer Ventures: The Memos That Didn't Get Away Frid...
- 11 Oct 2020
PCB、IC封装：设计与仿真分析: 全方位了解DDR 布线

TeamAllegro

本文要点： DDR 内存布线的重要性及布线时的关键注意事项。从扇出布线 (escape routing) 和端接，到布线和高密度互连 (HDI) 设计的布线技巧，有效进行 DDR 内存设计。高级PCB 设计工具的哪些功能有助于顺利完成设计。 space 在过去，人们认为计算机是一个用于完成特定目的的物体或设备，就像给微波炉或洗衣机连接插销一样。尽管在当今情况已经大有不同，但大多数人依然不了解我们每天实际上会使用多少计算能力。所有的智能手机、汽车系统和 IoT 设备都依赖计算能力来完成各自...
- 9 Oct 2020
Analog/Custom Design: Start Your Engines: Speed Up Your Analog Mixed-Signal Verification with Spectre X Simulator

Andre Baguenie

In this post, I will explain how you could speed up your mixed-signal verification with the Spectre X simulator. I will also cover how Spectre X can be set up for use in the AMS Designer flows
- 9 Oct 2020
Digital Design: Library Characterization Tidbits: Characterize Minimum Period for Memory Instance Using Liberate MX

HelenShi

In this blog, I will talk about the minimum period arc, which is a critical arc associated with the clock of a memory instance.
- 9 Oct 2020
Breakfast Bytes: Optimized Digital Design, Implementation, and Signoff on TSMC N3

Paul McLellan

At the recent TSMC OIP forum, Yufeng Luo presented Optimized Digital Design, Implementation, and Signoff on TSMC N3. He should know all the details. After all, he's the VP of R&D for the Innovus Implementation System, which is at the heart of...
- 9 Oct 2020
カスタムIC／ミックスシグナル: Virtuosity: Virtuoso Visualization and Analysisでのベクターファイルの読み込み

Custom IC Japan

IC6.1.8およびICADVM18.1より前のバージョンでは、適用されたスティミュラスとともにデジタル波形とアナログ波形を表示するには、デジタルソルバとアナログソルバの両方を使用してシミュレーションを実行する必要がありました。これは時間がかかるプロセスになる可能性があります。しかし現在は、デジタルスティミュラスファイルを直接ADEの波形ウィンドウであるCadence® Virtuoso® Visualization and Analysisに読み込むことができます。さらに、ス...
- 8 Oct 2020
Breakfast Bytes: Bessemer Ventures: The Memos That Didn't Get Away

Paul McLellan

Who is the oldest venture capital company in the world? It is almost certainly Bessemer Venture Partners, who were created as the venture arm of Carnegie Steel. The Bessemer process for making steel was the first economical process for making steel f...
- 8 Oct 2020
Analog/Custom Design: Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 3

Parula

Nowadays, it is more important than ever to use multiple test benches in a single design. Therefore, we are pleased to introduce more tips and tricks for the optimal use of the Virtuoso ADE Product Suite, which comprises of Virtuoso ADE Explorer, Virtuoso ADE Assembler, and Virtuoso ADE Verifier.
- 8 Oct 2020
Analog/Custom Design: Virtuoso ICADVM20.1 and IC6.1.8 ISR14 Now Available

Virtuoso Release Team

The IC6.1.8 ISR14 and ICADVM20.1 production releases are now available for download.
- 7 Oct 2020
Breakfast Bytes: TSMC OIP: Rent's Rule and Fast SerDes IP

Paul McLellan

Way back in the 1960s, E. Rent, who was working at IBM at the time, noticed a connection between the number of pins P on integrated circuits being use and the number of gates G on the integrated circuits. It was a power law, where the numbe...
- 7 Oct 2020
System, PCB, & Package Design : BoardSurfers: Training Insights: Creating Inter-Layer Checks Available in Constraint Manager

Shreyansh

In standard PCB designs, various masks and surface finishes require verification of proper clearances and coverage. The rigid-flex designs not only have the same mask and surface finish requirements but also have additional geometries, such as bend a...
- 6 Oct 2020
System, PCB, & Package Design : IC Packagers: Battening the Hatches After Going to Manufacturing

Tyler

When you send the initial version of your design for manufacturing, it’s a huge sense of accomplishment. Things are complete. All constraints have been met. When the part comes off the manufacturing line, it works. That is something to be proud...
- 6 Oct 2020
Academic Network: Two New Books for Your Bookshelf

Anton Klotz

With video conferences getting more and more popular it is a question how to present yourself most effectively to your counterparts, this starts with your outfit and ends with the background. Very advanced colleagues with powerful laptops use artific...
- 6 Oct 2020
Breakfast Bytes: Innovus Mixed Placer

Paul McLellan

It has been a dream for a long time to have a fully automated mixed placer that does a good job. In fact all physical design systems have had the capability for a long time, but designers were reluctant to use them on simple designs. When there were ...
- 6 Oct 2020
Breakfast Bytes: Jasper User Group 2020 Preview

Paul McLellan

The biggest gathering of formal verification engineers in the world takes place in a few weeks — the annual Jasper User Group is coming up on October 21st and 22nd. It has been branded under CadenceCONNECT, specialized meetings that take place ...
- 5 Oct 2020
Breakfast Bytes: Sunday Brunch Video for 4th October 2020

Paul McLellan

https://youtu.be/VZRwCBiexXQ Made in front of my TV Monday: The CHIPS Alliance Tuesday: NXP Glows in Tensilica HiFi Wednesday: GTC 2020 Thursday: Breakfast Bytes Update: Learning & Support, Undersea Datacenter Friday: Breakfast Bytes Up...
- 4 Oct 2020

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