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Breakfast Bytes: Rigid-Flex

Paul McLellan

Rigid-flex sounds like something that might be a Crossfit workout-of-the-day. But it is actually a way of doing electronic design for small form factors using flexible PCBs (typically along with some normal rigid PCBs too). But they require additiona...
- 6 Aug 2020
Breakfast Bytes: Why Attend CadenceLIVE Americas?

Paul McLellan

We renamed our user conference to CadenceLIVE (from CDNLive) just in time for it not to be live and to go virtual. The first conference is CadenceLIVE Americas coming up from August 11th to 13th. Registration is now open. This is a global event. Comi...
- 5 Aug 2020
PCB設計／ICパッケージ設計: BoardSurfers：17.4-2019 HotFix 007 for Electrical CAD-Mechanical CAD Library Creator について

SPB Japan

Library Creator 17.4-2019 HotFix 007のアップデートより、Templatesダイアログ全体に改良が加えられ、テンプレートを見つけて選択しやすくなりました。また、Propertiesウィンドウに多くの変更が加えられました。もう1つの注目すべき変更は、新しいルールをすばやく追加できるいくつかのボタンをConfigurationダイアログに追加したことです。ここから、変更の詳細についてご紹介します。ルールとコンストレイントを簡単に追加できます。ダイアログに新...
- 4 Aug 2020
PCB設計／ICパッケージ設計: 2020年5月リリース、OrCAD / Allegro 17.4-2019 HotFix 007 の新機能ハイライト

SPB Japan

OrCAD® 及び Allegro® のHotFix 007 (QIR 1)がCadence Downloadsからダウンロードできます。この新リリースでは、数多くの機能の改善や強化が行われており、その多くはお客様からのご要望、ならびに、我々が継続的に追求している使い易さとユーザーエクスペリエンスの向上というフォーカスに基づくものです。このリリースは、スプラッシュ画面においては”2020”と示されます。この最新バージョンを使い始めてみると、いたる所でちょ...
- 4 Aug 2020
System, PCB, & Package Design : BoardSurfers: Installation Know-How: Six Things You Need to Know Before Installing Cadence OrCAD and Allegro Products on Windows

Shikha Jain

Installation of software applications depends upon certain factors such as system configuration, the number of files getting installed, and network speed. Installation time is influenced by a change in any of these elements and hence individual...
- 4 Aug 2020
System, PCB, & Package Design : IC Packagers: Removing and Replacing an Area of a Design

Tyler

If you ever have the need to remove an area of your design, you may find it to be a more complex process than you would think. Shapes in that area will, if you select them with show element, want to pick up the entire shape. That may extend well outs...
- 4 Aug 2020
Breakfast Bytes: Accellera Functional Safety

Paul McLellan

This is my last post about DAC 2020. During DAC Accellera had a workshop about functional safety. In case you don't know, Accellera has a relatively new working group (WG) on Functional Safety. The chair is Cadence's Alessandra Nardi, who coi...
- 4 Aug 2020
Academic Network: Custom IC, Analog, and RF Design Training Deep Dive: Part 2

Kira Jones

Let’s continue exploring the training courses related to Custom IC, Analog, and RF Design. We’re going to be introducing some new courses and some new tools in these training recommendations. It is recommended that you start with Custom I...
- 3 Aug 2020
Breakfast Bytes: DAC 2020: Chips in 2030

Paul McLellan

In 2015, soon after I rejoined Cadence, I went to IEDM, the International Electron Devices Meeting. That year it was in Washington DC. I paid for most of the trip myself since I'd already booked the flights and hotels months in advance to get goo...
- 3 Aug 2020
カスタムIC／ミックスシグナル: Virtuosity: Analog Design Environmentにおけるポストレイアウト関連の機能強化トップ３

Custom IC Japan

今日のブログでは、ポストレイアウトフローの最新の機能強化について説明します。これらの機能強化により、回路図とポストレイアウトの名前のマッピング、端子電圧のプロット、DSPFファイルのスイープなど、長年の問題の多くが解決されます。このブログは、Virtuoso®ADE Assembler、Virtuoso®ADE ExplorerおよびVirtuoso® Visualization and Analysisのリリースされたばかりの機能をカバーするために、週に2回（火曜日と...
- 2 Aug 2020
Analog/Custom Design: Virtuoso Meets Maxwell: How Come There is No Mention of Wirebonded ICs?

Steve PDK Lee

Hello and welcome to Virtuoso Meets Maxwell. If you are a regular reader you might be thinking to yourself, “There’s not a lot about wirebonds in the Virtuoso RF Solution and I’m interested in wirebond support.” That’s a great observation and it’s time for bringing wirebonds into the spotlight.
- 2 Aug 2020
Breakfast Bytes: Sunday Brunch Video for 2nd August 2020

Paul McLellan

www.youtube.com/watch Made in "Indonesia" (camera me) Monday: Open Source Hardware Tuesday: DAC 2020: The State of the Industry Wednesday: DAC 2020: Open-Source EDA Thursday: Recruiting and Onboarding during WFH Friday: DAC 2020: TSMC ...
- 2 Aug 2020
PCB、IC封装：设计与仿真分析: 如何在PCB设计中解决最新的PCIe 信号完整性挑战

Sigrity

图 1：基于 PCIe 的高性能显卡为了应对计算密集型工作负载，数据中心行业领域趋势正在向异构计算发展。该趋势同时推动着相应软件解决方案的开发，以便在具有不同核心和内存配置的多台计算机之间分配工作负载。伴随着高速计算而来的是对高速数据传输的需求：PCIe 总线是一种针对数据传输的关键性促成技术，其最新一代标准（4.0/5.0）大大提升了带宽并降低了延迟。尽管从数据吞吐量的角度来看这很有吸引力，但是这些性能方面的提升也带来了巨大的信号完整性（SI）设计挑战。为了应对 PCIe 4.0/5.0...
- 1 Aug 2020
Life at Cadence: My Life at Cadence Video Series: Alessandra Nardi

Mary Kasik

Cadence recently interviewed five of our amazing women engineers for a new video series titled “My Life at Cadence”! This fifth video features Alessandra Nardi, software engineering group director, Automotive Solutions...
- 31 Jul 2020
Breakfast Bytes: DAC 2020: TSMC Keynote

Paul McLellan

The opening keynote at DAC was TSMC's Chief Scientist Philip Wong. That's clearly not nearly enough work, so he's a professor at Stanford, too. As I said in my post DAC Preview 2020, I've seen a version of this presentation befor...
- 31 Jul 2020
PCB設計／ICパッケージ設計: Cadence PCB Viewers 2019を使用して、OrCAD回路図、ボード、ICパッケージを無料ですばやく表示

SPB Japan

OrCAD® 製品一式をインストールすることなく、OrCAD Captureの回路図、レイアウト、またはICパッケージのデザインをすぐに表示したいと思いませんか？ OrCAD Capture, PCB Editor, または Allegro Package Designer Plusで作成されたデザインデータへの読み取り専用でのアクセス手段を手に入れたいですか？その願いは実現されました。 17.4-2019 HotFix 008では、OrCAD® Captu...
- 30 Jul 2020
PCB設計／ICパッケージ設計: BoardSurfers: Allegro In-Design Impedance Analysis：配線済みデザインをすばやくスクリーニング

SPB Japan

すべての配線信号トレースを解析せずにプリント基板(PCB)を製造したことがありますか?ほとんどの設計者は「はい、いつも」と言うでしょう。トレースの幅と間隔はコンストレイントによって設定されており、多くの設計者は、これらのコンストレイントが設計に必要なマージン内のインピーダンス値に収まることを確認する時間がありません。基板上の高速トレースは最も慎重にレイアウトされていますが、残りのトレースは、ルーティング後に検査なしで製造に送られることがよくあります。 Sigrity ハイブリッドソ...
- 30 Jul 2020
Analog/Custom Design: Virtuosity: In the Line of Veri-Fire - Episode 3

Team ADE Verifier

Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso ADE Verifier and learn about its various whys and hows. In this series, Dr. Walter Hartong, a Product Engineering Architect at Cadence, will be answering some frequently asked questions on Virtuoso ADE Verifier. Stay tuned for some interesting explanations and solutions!
- 30 Jul 2020
Digital Design: It May Sound Unbelievable, But Do You Know You Can Relax While Analyzing Timing Results in Genus? Want to Check?

Neha Joshi

Gone are the days when analyzing timing reports of the design used to take hours! We understand, your designs are complex and so is timing analysis. We cannot change the design, but we have made the timing analysis process easier for you during the synthesis stage.

Are you ready to relax? Stop at channel-based Training Bytes on “Useful scripts for Timing Report Analysis” at https://support.cadence.com (Cadence login required…
- 30 Jul 2020
Digital Design: Library Characterization Tidbits: Deconstructing the Mechanics of Liberate MX Constraint Probing

Neha Garhwal

Thinking about how Liberate MX characterizes the constraint arcs, how the probe locations are picked up by the tool, what are the various controls associated with probing? Read the blog to find the answers.
- 30 Jul 2020
Breakfast Bytes: Recruiting and Onboarding During WFH

Paul McLellan

My son has just been recruited into a new job in New York. He told me that it is a weird experience being recruited and starting in a company during the work-from-home (WFH) era. He doesn't know anyone, he hasn't met any of his co...
- 30 Jul 2020
PCB設計／ICパッケージ設計: IC Packagers: ボンドフィンガー・ソルダーマスク開口部の新しいオプション

SPB Japan

ワイヤーボンドパッケージを設計する場合、パッケージ基板層のボンドフィンガーとリングはソルダーマスク層を通して露出させる必要があります。そうでければ、ワイヤーをそれらに結合することはかなり難しくなります。以前に “バウンドレスバウンティオブバウンディングシェイプ” (バウンディングシェイプの際限なき恩恵)” で Create Bounding Shape ツールについて話しました。ボンドフィンガーには、ソルダーマスクレイヤーを介した露出に関して、いくつか...
- 30 Jul 2020
PCB設計／ICパッケージ設計: IC Packagers: “バウンドレスバウンティオブバウンディングシェイプ” (バウンディングシェイプの際限なき恩恵)

SPB Japan

この英文タイトルはまるで早口言葉ですね。早口で3回繰り返せますか？さて、今回のトピックスはAllegro® Package Designer及びSiP LayoutのShapesメニューにある"Create Bounding Shapes"ツールです。この機能について最初にお話したのは、実は数年前のことです。このコマンドの歴史に興味がおありでしたら、こちらのリンク(※英文)からその時の記事をご覧いただけます。このコマンドが最初にツールに追加された背景は、とあるお客様...
- 30 Jul 2020
Life at Cadence: The Returnship Journey: Part 2

Ale Costa

Sharon Munoz’s Journey Stepping away from an engineering career to focus on caring for family can be a tough decision, but it doesn’t have to be the end of a career. New returnship programs, like the one offered by Cadence, provide a gre...
- 29 Jul 2020
System, PCB, & Package Design : Quickly View Schematic Designs, Boards, and IC Packages for Free Using Cadence PCB Viewers 2019

AllegroReleaseTeam

Do you want to quickly view a schematic, layout, or IC package without installing the complete OrCAD product suite? Get read-only access to design data created in OrCAD Capture, PCB Editor, Allegro Package Designer Plus? With 17.4-2019 HotFix...
- 29 Jul 2020

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