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Latest Blog Posts

  • System, PCB, & Package Design : IC Packagers: Plating Bars versus Edge Connections

    Tyler
    Tyler
    I think every traditional package designer understands what a plating bar is and the purpose it serves. There to provide electric current during the manufacturing process, each net is connected out to the perimeter of the BGA, which allows for the cu...
    • 28 Jul 2020
  • Breakfast Bytes: DAC 2020: The State of the Industry

    Paul McLellan
    Paul McLellan
    Monday was the first day of DAC, the Design Automation Conference. Of course, like everything else it was fully virtual. Having been in EDA for nearly 40 years, my usual experience at DAC was not being able to walk more than about ten feet without ru...
    • 28 Jul 2020
  • カスタムIC/ミックスシグナル: Start Your Engines: CLIPSを使ってSoC検証用にポータブルなVirtuoso IPを生成する

    Custom IC Japan
    Custom IC Japan
    Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 ミックス...
    • 28 Jul 2020
  • カスタムIC/ミックスシグナル: Start Your Engines:デジタル機能検証フローのためにAMS UNL IP をエクスポートする

    Custom IC Japan
    Custom IC Japan
    Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。   IP再利...
    • 27 Jul 2020
  • 定制IC芯片设计 : Virtuoso Meets Maxwell: 单一流程的共同目标,优化射频设计流程

    michaelthompson
    michaelthompson
    七个月前,我就提出射频设计流程需要不断变化和创新的需求。IP设计跨越多个分立的、没有联系的工具,容易导致生产和设计人为错误,也减慢了设计过程,这会造成设计工程师们只专注追踪编辑和更新,而忽略了创新。 在您当前的设计流程中,追踪和确保正确的S参数文件是一件必须要做的事情,这看上去也像是一项工作,但是您是想持续做笔记,还是做设计呢?为了解决您的这些困扰,我们发布了 Virtuoso RF解决方案,它可用于处理笔记问题,而设计师们只需专注于设计。
    • 27 Jul 2020
  • Breakfast Bytes: Open Source Hardware

    Paul McLellan
    Paul McLellan
    Open-source software has revolutionized many aspects of software development. But I believe it has a business-model problem. It is largely successful in supply chains where someone wants to "commoditize their complements". It reminds me of ...
    • 27 Jul 2020
  • カスタムIC/ミックスシグナル: Virtuosity: Sharing Custom SKILL Calculator Functions

    Custom IC Japan
    Custom IC Japan
    計算を実行するすばらしいSKILL を記述し、それを広く世間に知らしめたいと思ったことがありますか?または、特定の計算を実行するCalculator関数が本当に必要なのに、Cadence がそのような関数をCalculator または Expression Builderで提供していないことがありますか?  これらの問題に対処するために、私たちは、新しい Custom IC Calculator SKILL Function Library  を Cadence ...
    • 27 Jul 2020
  • PCB、IC封装:设计与仿真分析: 如何优化板载去耦电容

    Sigrity
    Sigrity
    本文翻译、转载自2019年9月发布于Signal Integrity Journal的文章《On-Board Decoupling Capacitor Optimization》。 电源完整性(PI)分析的目的是确保系统中所有芯片供电充足且稳定。随着印刷电路板日益复杂、系统尺寸持续减小,确保关键芯片的电源稳定变得越来越重要。设计阶段尽早优化其位置和数值将降低后期设计变更或电路板重新设计的风险。通过将电源网络的阻抗保持在特定目标[1]以下,可以确保关键芯片的供电稳定。 去耦电容可以在一定频率范围内...
    • 25 Jul 2020
  • Life at Cadence: My Life at Cadence Video Series: Hao Ji

    Mary Kasik
    Mary Kasik
    Cadence recently interviewed five of our amazing women engineers for a new video series titled “My Life at Cadence”! This fourth video features Hao Ji, senior engineering group director in the Signoff Group at Cad...
    • 24 Jul 2020
  • Academic Network: Custom IC, Analog, and RF Design Training Deep Dive: Part 1

    Kira Jones
    Kira Jones
    We’re continuing the blog series that is taking the top 15 Online Training courses among students and professors and breaking it down into their different technical areas and sharing the supporting courses that go along with them. We start...
    • 23 Jul 2020
  • Analog/Custom Design: Virtuoso Video Diary: Enhancements in Reliability Analysis

    Udit Rajput
    Udit Rajput
    Read through this blog to know more about the enhancements made to the reliability analysis in Virtuoso ADE Assembler and Virtuoso ADE Explorer over a couple of IC6.1.8 and ICADVM18.1 ISR releases.
    • 23 Jul 2020
  • カスタムIC/ミックスシグナル: Virtuosity: Maestro Plotting Templateの紹介

    Custom IC Japan
    Custom IC Japan
    波形、プロット、グラフ、メジャメント、マーカー、全て回路設計者のみなさんが日常的に接する要素だと思います。Wavescan時代から長い日々を経て、IC6.1.8及びICADVM18.1のリリースから、グラフとプロットのより優れたツール Virtuoso® Visualization and Analysisに、更に強力な機能が加わりました。 今までのVirtuoso® ADE Explorer や Virtuoso® ADE Assembler&nb...
    • 21 Jul 2020
  • System, PCB, & Package Design : BoardSurfers: Everything You Need to Know About Fixed Fillets/Teardrops

    BarbS
    BarbS
    First, teardrops and fillets are interchangeable words in PCB design, and both terms are used here in this post. Second, I’m going to go over fixed fillets from start to finish so you can avoid the problem when you are ready for Fab...
    • 21 Jul 2020
  • System, PCB, & Package Design : IC Packagers: Staggering Shape Outlines

    Tyler
    Tyler
    Having coincident edges shared across multiple layers is frequently not a desirable situation to be in. Just as we don’t appreciate degassing holes at the same position on adjacent layers – which can lead to dips or valleys in the finishe...
    • 21 Jul 2020
  • Digital Design: Voltus Voice: Power Signoff Ramp-Up RAKs – Hello Electrical, Meet Thermal!

    Ramesh Sharma
    Ramesh Sharma
    This blog introduces the Voltus-Celsius Electro-Thermal Analysis RAK that will give you an accelerated start to achieve accurate co-analysis of a power-grid network on a chip-package-PCB system.
    • 20 Jul 2020
  • Analog/Custom Design: Start Your Engines: Seamlessly Reusing Advanced Digital Testbenches in AMS UNL

    Rick Sanborn
    Rick Sanborn
    The Virtuoso Advanced Testbench Reuse flow with Xcelium eases the painful process of SV UVM testbench reuse in the AMS UNL flow. Continue reading to know more.
    • 20 Jul 2020
  • Analog/Custom Design: Virtuoso Meets Maxwell: Cross-Fabric Electromagnetic Extraction - Eliminating the Tedious Work of Merging IC, Package, and Board

    jgrad
    jgrad
    With modules coming from multiple platforms, cross-fabric EM analysis becomes an important requirement in Virtuoso RF Solution. The Electromagnetic Solver assistant has an easy solution available for this.
    • 19 Jul 2020
  • PCB、IC封装:设计与仿真分析: 极致PCB设计全流程 I 技巧五:布线技巧

    SDA China
    SDA China
    布线阶段如何减少重复性机械劳动?让工具处于最佳使用状态,为您赢得设计思考和规划的时间。 布线设计并非连连看,熟悉布线设置、实现成组布线,都能使布线工作事半功倍,从而交付高质量的PCB设计作品。 微信后台回复关键词“PCB全流程”即可get完整课程计划与资料汇总页面链接,快快添加收藏吧~ 点击图片可查看清晰大图,点击此处下载PDF版完整内容 “极致PCB设计全流程网课计划”第五期实战直播 识别下图二维码,立刻报名! space 相关内容...
    • 18 Jul 2020
  • PCB、IC封装:设计与仿真分析: 极致PCB设计全流程 I 基础五:布线规划

    SDA China
    SDA China
    布线阶段如何减少重复性机械劳动?让工具处于最佳使用状态,为您赢得设计思考和规划的时间。 布线设计并非连连看,而是设计思路的物理实现,有了设计思路+系统规划,才能交付高质量的PCB设计作品。 微信后台回复关键词“PCB全流程”即可get完整课程计划与资料汇总页面链接,快快添加收藏吧~ 点击图片可查看清晰大图,点击此处下载PDF版完整内容 极致PCB设计全流程网课计划”第五期实战直播 识别下图二维码,立刻报名! space 相...
    • 18 Jul 2020
  • Digital Design: Library Characterization Tidbits: Rewind and Replay - 2

    Jommy
    Jommy
    A recap of the blogs published in the Library Characterization Tidbits blog series.
    • 17 Jul 2020
  • Verification: Troubleshooting Xcelium Errors/Warnings with xmhelp/xmbrowse and Cadence Support Portal

    SumeetAggarwal
    SumeetAggarwal

    I joined Cadence in July 2000 and was immediately put on a three-month training to learn and understand the simulator tools. There were formal training sessions, and I had a mentor whom I could ask all my queries. But most of the time, I was on my own, as "learning by doing" was the motto of my mentor. Today, after completing 20 years at Cadence, I can tell you that it works great, especially in cases where the tool is…

    • 17 Jul 2020
  • Breakfast Bytes: Celsius and Voltus: 2+2=5

    Paul McLellan
    Paul McLellan
    I recently attended a webinar presented by Rajat Chaudhry, who is a Product Engineering Director in the Multi-Physics System Analysis Group. The title was Chip Thermal Analysis with Celsius Thermal Solver. The word "chip" is important. Celsius can be...
    • 17 Jul 2020
  • Analog/Custom Design: Virtuosity: In the Line of Veri-Fire - Episode 2

    Team ADE Verifier
    Team ADE Verifier
    Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso ADE Verifier and learn about its various whys and hows. In this series, Dr. Walter Hartong, a Product Engineering Architect at Cadence, will be answering some frequently asked questions on Virtuoso ADE Verifier. Stay tuned for some interesting explanations and solutions!...
    • 16 Jul 2020
  • Breakfast Bytes: Clarity, Sigrity, EMX, and AWR: So Many EM Solvers to Choose From…

    Paul McLellan
    Paul McLellan
    Cadence has multiple electromagnetic (EM) technologies within its product portfolio as of today.  Some came via acquisition and others were created internally.  With a wide breadth of EM simulation and analysis tools within the Cadence prod...
    • 16 Jul 2020
  • Academic Network: Great Collaboration on Teaching Verification with Bosch Sensortec and HTW Dresden

    Anton Klotz
    Anton Klotz
    The HTW Dresden - University of Applied Sciences offers several courses in the area of design for digital circuits. In addition to synthesis, verification has become an important topic in recent years that HTW Dresden has been focusing on. In their o...
    • 15 Jul 2020
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