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Life at Cadence: Showing Support for Our Veterans at Cadence

Ryan Robello

Cadence and our employees were proud to show appreciation for our Veteran employees, their families, and all who have served the United States this Veterans Day. Honoring our military's personnel, Cadence observed Veterans Day as a holiday in the U.S...
- 30 Nov 2022
Computational Fluid Dynamics: I’m Samuel Afari and This Is How I Mesh

John Chawner

Hi, I’m Samuel Afari and I’m a CFD Applications Engineering Intern at Cadence. I am currently a PhD candidate at Embry-Riddle Aeronautical University in Daytona Beach, Florida. I also did my MSc in Aerospace Engineering at the same school...
- 30 Nov 2022
Verification: Understanding Latency versus Throughput

Corporate

One of the effects of adopting a High Level Synthesis design methodology is that the barrier between "Systems designers" and "Hardware designers" is substantially reduced if not totally eliminated. Suddenly, both "Systems designers" and "Hardware de...
- 30 Nov 2022
Breakfast Bytes: November Update: Power, TOP500, the Kaufman Dinner, Fred Brooks, and an Award

Paul McLellan

Today is the last day in November, amazingly, and since I was on vacation last Friday, today is my regular monthly update covering topics that don't justify a whole post on their own or that are updates to a previously published post. Kaufman Din...
- 30 Nov 2022
Spotlight Taiwan: Cadence與聯電共同開發認證的毫米波參考流程達成一次完成矽晶設計

candyyu

聯電射頻晶圓設計套件(RF FDK)和Cadence RF方案協助其共同客戶 - 聚睿電子達成卓越 5G 射頻設計成果 Cadence與聯電宣布雙方合作經認證的毫米波參考流程，成功協助亞洲射頻IP設計的領導廠商聚睿電子(Gear Radio Electronics)，在聯電28HPC+ 製程技術以及Cadence® 射頻(RF)解決方案的架構下，達成低噪音放大器 (LNA) IC一次完成矽晶設計(first-pass silicon success) 的非凡成果。經驗證的聯電28HP...
- 30 Nov 2022
Life at Cadence: Smart Manufacturing: What’s Needed for the Industrial Intelligence Revolution?

Ben Gu

Smart manufacturing – the use of nascent technology within the industrial Internet of things (IIoT) to address traditional manufacturing challenges – is leading a supply chain revolution, resulting in smart, connected, and intelligent env...
- 29 Nov 2022
Verification: Training Insights – Webinar – Automating Bug Tracking with Verisium Debug and Python

ManishaP

Join Cadence Training and Principal Application Engineer Daniel Bayer for this free technical training webinar.

The Verisium Debug Platform is optimized for scalability, supporting debugging of simulation runs and emulation, where support for loading large source files and handling huge amounts of probe data is a must.

In this Training Webinar, you’ll learn how to automate your debug experience using the Verisium Debug…
- 29 Nov 2022
Analog/Custom Design: Virtuoso Meets Maxwell: Top of the PoPs! By Exporting the Package Footprint in Virtuoso

VRF Knight

I’m back again, it has been a while, but guess what… I have a lot of goodies to share with you. Since last time I posted a blog, our Virtuoso System Design solutions have gone through a lot of enhancements, and more automations have been accomplished. You may already have read our blog, Virtuoso Meets Maxwell: Getting Your Existing SiP File Into Virtuoso RF Solution, which covers how you can bring your existing SiP design…
- 29 Nov 2022
Computational Fluid Dynamics: Webinar on Dec 1: Advanced Pre-Processing and Unstructured Meshing in Fidelity 2022.2

John Chawner

Join us for a CadenceTECHTALK (aka webinar) to learn how the upcoming release of Fidelity CFD software significantly extends the capabilities of our pre-processing and unstructured meshing solutions. We'll demonstrate: Better performance for lar...
- 28 Nov 2022
Spotlight Taiwan: Cadence AWR 電磁與熱分析功能實現完整RF 應用

candyyu

【技術講堂影片回顧】為取得競爭激烈的5G/無線市場先機，RF技術成為兵家必爭之地，為協助客戶實現完整且全面的RF工作流程解決方案，Cadence打造RF工作流程創新，導入RF整合為工程團隊提升生產力。本次線上研討會影片回顧，將帶您一窺Cadence Clarity 3D 求解器(Solver) 和Celsius 熱求解器(Thermal Solver) 無縫整合導入Cadence AWR環境平台，透過內建的電磁與熱分析，不受限制的直接從內部解決大規模且複雜的RF系統，幫助客戶減少周...
- 28 Nov 2022
Analog/Custom Design: Virtuosity: Custom IC Design Flow/Methodology - Post-Layout Circuit Simulation and GDSII Generation

Ashish Patni

Read this blog for getting an overview of post-layout circuit simulation & GDSII generation.
- 23 Nov 2022
Life at Cadence: System Verification of Arm Neoverse V2-Based SoCs

Corporate

The world around us has become data-centric; everything needs data, from navigation maps in vehicles to medical chatbots to autonomous cars. We are using data to solve complex problems and decision-making. The beauty is more data leads to better per...
- 22 Nov 2022
Digital Design: Voltus Voice: Voltus-Sigrity Collaboration Fuels System Innovation

Anshika Gahlaut

Learn how the Voltus-Sigrity X integrated solution can help you achieve faster system-level power integrity analysis and closure.
- 21 Nov 2022
Life at Cadence: Cadence Optimality AI Removes Simulation’s Biggest Bottleneck: Humans

Ben Gu

A core part of what we do at Cadence comes from an inescapable truth: designing and fabricating a silicon chip is an increasingly complex, time-consuming, and therefore expensive process. At every step of that process there are decisions to be made....
- 21 Nov 2022
RF /マイクロ波設計: μWaveRiders:最新の AWR Design Environment オプティマイザでゴールを決める

RF Design Japan

The Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題は、Cadence AWR Design Environmentのリリースのハイライト、機能ビデオとスポットライト、ソフトウェアのヒント、コツ、カスタマイズによって異なります。最新のμWaveRidersのブログ投稿についてのメール通知を受け取りたい方はSubscribe をして下さい。 AWR Design Env...
- 21 Nov 2022
Verification: How to Verify Complex PIPE Interface Based PHY Designs?

Nehal Patel

High-end SOC architectures today requiring more area and higher speed to transfer and process data. To fulfill this requirement, protocol such as PCIe, USB, DP, SATA and USB4 are regularly being updated. Most critical part of the high-speed interface is the Physical (PHY) layer of the protocol where the actual signaling happens. In addition to signaling, the PHY also takes care of some of the processing to reduce errors…
- 21 Nov 2022
RF Engineering: μWaveRiders: Scoring Goals with the Latest AWR Design Environment Optimizer

TeamAWR

AWR V22.1 software introduces the Pointer-Hybrid optimization method which uses a combination of optimization methods, switching back and forth between methods to efficiently find the lowest optimization error function cost. The optimization algorithm automatically determines when to switch to a different optimization method, making this a superior method over manual selection of algorithms. This method is particularly…
- 21 Nov 2022
Breakfast Bytes: Sunday Brunch Video for 20th November 2022

Paul McLellan

https://youtu.be/gLQbSlICCaE Made in Munich Englischergarten (camera Carey) Monday: Tensilica for Automotive Radar Tuesday: Passage: Wafer-Scale Programmable Photonic Communication Wednesday: Software 2.0 Thursday: Offtopic: Old Programming Languages...
- 20 Nov 2022
System, PCB, & Package Design : IC Packagers: Training Insights: What's New in the Allegro X Advanced Package Designer Course

DanGerard

The Allegro X Advanced Package Designer course provides all the essential training required to start working with Allegro X Advanced Package Designer. The course covers all the design tasks, including importing IC data, BGA generation and connec...
- 18 Nov 2022
Verification: How Renesas Reduced Automotive SoC Verification Time

Reela Samuel

The automotive world is conquering new technological heights, piggybacking on advanced semiconductor components. A typical vehicle has around 1,400 semiconductor components, and the numbers are expected to go higher as vehicles become more intelligent and autonomous. The ecosystem change in the automotive world has mutated the demand patterns for automotive chips, resulting in the growing demand for purpose-driven applications…
- 17 Nov 2022
Life at Cadence: Cardo Brings Cutting-Edge Audio Connectivity to Groups in Motion

Corporate

Motorcyclists riding through extreme conditions need a communication device that’s as rugged as the road ahead of them. That’s where Cardo Systems comes in, with their tough, dependable, and durable communicators. Most of all, their commu...
- 17 Nov 2022
Breakfast Bytes: Old Programming Languages

Paul McLellan

This is the last day before a break. Tomorrow I fly to Germany for CadenceLIVE Europe, and I will be taking a week of vacation after that to visit Berlin, a city I've somehow never visited. Breakfast Bytes will next appear on November 30th. As us...
- 17 Nov 2022
Breakfast Bytes: Software 2.0

Paul McLellan

I recently came across the idea of "software 2.0". I was watching a Lex Fridman interview with Andrej Karpathy called Andrej Karpathy: Tesla AI, Self-Driving, Optimus, Aliens, and AGI | Lex Fridman Podcast #333. I'll embed the podcast a...
- 16 Nov 2022
Life at Cadence: Effective Measurement Is the Key to Meeting Environmental Sustainability Goals in Data Centers

Neil Zaman

Hyperscale compute, using high-performance connected processors, continually transforms our lives as more and more applications rely on this type of compute, and at the heart of this hyperscale revolution are data centers. It is estimated that an eq...
- 15 Nov 2022
Breakfast Bytes: Passage: Wafer-Scale Programmable Photonic Communication

Paul McLellan

One of the most intriguing chips presented at HOT CHIPS earlier this summer was Lightmatter's Passage. I covered it briefly in my summary post about the conference HOT CHIPS Day 1: Hot Chiplets. Steve Klinger, Lightmatter's VP of product, presented a...
- 15 Nov 2022

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