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System, PCB, & Package Design : Clarity Encrypted Connectors!

Sherry Hess

Cadence Clarity 3D Solver supports encrypted component models! Using this functionality, vendors can supply their 3D components, such as connectors, to end customers without revealing the physical IP of these designs. The first connector vendor to take advantage of this functionality is Japan Aviation Electronics (JAE),
- 21 Aug 2022
Breakfast Bytes: Sunday Brunch Video for 21st August 2022

Paul McLellan

https://youtu.be/YWpcaIEkw7M Made at Lake Tahoe (camera Carey) Monday: 75 Years of Indian Independence Tuesday: PK: A Museum for the Biggest Telecommunication Hub in the World Wednesday: UCIe PHY and Controller—To Die For Thursday: Whatever Hap...
- 21 Aug 2022
System, PCB, & Package Design : BoardSurfers: Training Insights: User Interface Enhancements for Allegro Layout Editors

ACat299612

If you have seen any images or demonstrations of the 17.4-2019 release, the GUI may look ...
- 19 Aug 2022
Spotlight Taiwan: 2022 CadenceLIVE Taiwan 9月1日實體回歸隆重登場

candyyu

半導體產業是電子資訊產業的火車頭，與全球經濟高度連動，面臨全球景氣可能趨緩，半導體產業也將面臨成長的挑戰。EDA為研判半導體景氣的風向球，如何逆風引領全球經濟重啟，未來動向與展望備受矚目! 一年一度半導體與EDA年度盛事 - CadenceLIVE Taiwan 台灣使用者大會即將登場，於9/1(四)於新竹喜來登飯店舉行，並以實體方式隆重回歸。CadenceLIVE Taiwan今年聚焦『Intelligence. Designed.』，匯聚各領域菁英、半導體科技研發人員、電子設計社...
- 19 Aug 2022
Life at Cadence: Collaborating to Enable Data Centers, Automotive, Consumer, and AI/ML Technologies

fschirrmeister

It takes the proverbial village to build complex chips and systems these days. Imagination and Cadence are critical parts of the ecosystem that build many of the technologies that make our life as consumers more productive, comfortable, and safe. In ...
- 18 Aug 2022
Breakfast Bytes: Whatever Happened to 450mm Wafers?

Paul McLellan

When I started at VLSI Technology in the early 1980s, our fab used 5" wafers (150mm, also called 6" sometimes). At some point, VLSI converted to 8" (200mm) wafers. This is not easy to do without taking the fab down completely since you...
- 18 Aug 2022
Computational Fluid Dynamics: Experience the CFD Velocity Contours With Virtual Reality

Veena Parthan

Virtual reality in CFD, especially for post-processing the simulation results, can help users interact with the model to study the physics and find ways to improvise the design.
- 18 Aug 2022
カスタムIC／ミックスシグナル: Spectre Tech Tips: Spectre X EMIR Voltus-XFiの紹介

Custom IC Japan

Spectre® 21.1 ISR8とVirtuoso® IC6.1.8 ISR26（またはICADVM 20.1 ISR26）の組み合わせから、新しいプロダクトVoltusTM-XFi Custom Power Integrity Solutionが導入されました。このプロダクトは、抽出（QuantusTMを使用した）、シミュレーション（ADEとSpectreを使用した）およびデバッグ環境が統一されたコックピットを提供するトランジスタ・レベルのエレクトロマイグレーションとIRド...
- 17 Aug 2022
Breakfast Bytes: UCIe PHY and Controller—To Die For

Paul McLellan

UCIe is the Universal Chiplet Interconnect Express, a type of die-to-die (d2d) serial interconnect. This was announced in March, earlier this year, and I wrote about it at the time in my post Universal Chiplet Interconnect Express (UCIe). I happened ...
- 17 Aug 2022
Academic Network: Cadence Contributes to China Postgraduate IC Innovation Competition

Tracy Zhu

Students are full of wisdom, energy and courage to pursue their dreams. China Postgraduate IC Innovation Competition is one of the series of the Postgraduate Innovation and Practice Competition; it is a team-based, creative, practice, activity...
- 16 Aug 2022
Breakfast Bytes: PK: A Museum for the Biggest Telecommunication Hub in the World

Paul McLellan

In 1920, the little building below was the biggest telecommunication hub in the world. It was the telegraph, rather than the telephone, but 14 cables that circled the globe terminated here at Porthcurno, in Cornwall at the end of that long ...
- 16 Aug 2022
Analog/Custom Design: Virtuoso Meets Maxwell: Completing the Virtuoso RF Solution Assisted Flow

kgjudd

In my last blog, Getting Your Existing SiP File Into Virtuoso RF, I talked about the new enhancements in ICADVM20.1 ISR25 for Virtuoso RF Solution. At the end of the blog, I told you about the Fully Assisted Roundtrip flow, which includes importing SiP files that are compatible with the Virtuoso RF Solution assisted import flow into the Virtuoso platform. Let's examine how the Fully Assisted Roundtrip flow works in this…
- 16 Aug 2022
Computational Fluid Dynamics: 10 Steps from CAD to CFD Using Fidelity Pointwise

Veena Parthan

The 10 steps mentioned in this article can ease the preprocessing step (primarily importing CAD files and meshing) for a CFD solution using the Fidelity Pointwise meshing tool.
- 15 Aug 2022
Verification: Achieve 80% Less Late-Stage RTL Changes and Early RTL Bug Detection

Vinod Khera

It has become challenging to ensure that the designs are complete, correct, and adhere to necessary coding rules before handing them off for RTL verification and implementation. RTL Designer Signoff Solution from Cadence helps the user identify RTL bugs at a very early development stage, saving a lot of effort and cost for the design and verification team. Our reputed customers have confirmed that using RTL signoff for…
- 15 Aug 2022
System, PCB, & Package Design : Japan Aviation Electronics is First to Support IP Protected Models for Cadence Clarity 3D Solver

Sigrity

With the latest release (Sigrity and Systems Analysis 2022.1 HF2) of Clarity 3D Solver, support for encrypted component models is now available. With this functionality, vendors that supply 3D components, such as connectors, can now merge their...
- 15 Aug 2022
カスタムIC／ミックスシグナル: Start Your Engines: SimVision MSを用いたインターフェイス・エレメントのデバッグのための革新的かつ効率的なアプローチ

Custom IC Japan

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 AMSエンジニアのみ...
- 15 Aug 2022
SoC and IP: Building Robust PCI Express IP Solutions: Compliance and Beyond

Arif Khan

Discover PCIe

Going from draft specification to being listed as compliant on the integrators list by PCI-SIG is a multiple-year journey. The preliminary PCIe® 5.0 specification was announced in June 2017, with the final specification released in May 2019 and the first official compliance workshop conducted in April 2022. This represents the complexity of the products being built and the ecosystem required to support them…
- 15 Aug 2022
Breakfast Bytes: 75 Years of Indian Independence

Paul McLellan

Today is Independence Day in India. But more than that, today, in 2022, it is the 75th anniversary of India's independence from Britain in 1947. For those of you whose knowledge of Indian history is even less than mine, one important aspect of indepe...
- 15 Aug 2022
Breakfast Bytes: Sunday Brunch Video for 14th August 2022

Paul McLellan

https://youtu.be/8_-4j3lnjZI Made in Stevens Creek County Park Monday: Metaverse for Semiconductor Design: What to Expect? Tuesday: Commercial Air Travel at Mach 1.7 Wednesday: Electronics and Its Role in Climate Change Thursday: Convergenc...
- 14 Aug 2022
Verification: JEDEC UFS 4.0 for Highest Flash Performance

Yeshavanth BN

Speed increase requirements keep on flowing by in all the domains surrounding us. The same applies to memory storage too. Earlier mobile devices used eMMC based flash storage, which was a significantly slower technology. With increased SoC processing speed, pairing it with slow eMMC storage was becoming a bottleneck. That is when modern storage technology Universal Flash Storage (UFS) started to gain popularity.

UFS is…
- 11 Aug 2022
Breakfast Bytes: Convergence of Mechanical and Electronics in Automotive Design

Steve Brown

Someone once said, “Mechanical engineers design the automotive machine, electrical engineers design the navigation brains, and civil engineers design the roadways.” Implied here could be the idea that these engineering disciplines work s...
- 11 Aug 2022
Life at Cadence: ADAS, Infotainment, Functional Safety, and System Design: How Cadence is Ready for Automotive Electronics Revolution

Vinod Khera

Cadence Automotive Innovations Platform: From Concept to Silicon to System The automotive industry has been one of the most dynamic due to the accelerated rise of new technologies and changing customer preferences. It is going through an electronic r...
- 11 Aug 2022
Digital Design: Training Insights - Achieving a Holistic Power-Aware Design by Getting Low-Power Right

sakshin

This blog post mentions the Cadence Low Power Solution, a design-to-signoff methodology, that helps you implement several low-power techniques to reduce both dynamic and leakage power during synthesis and design implementation. Formal verification can be run to ensure the functionality of a low-power design.
- 10 Aug 2022
Breakfast Bytes: Electronics and Its Role in Climate Change

fschirrmeister

Sustainability has become a “scorching topic” (pun intended) in discussions I have with customers and ecosystem partners. It is now vital to many corporations as part of what many they report on “Environmental, Social, and Governanc...
- 10 Aug 2022
Analog/Custom Design: Knowledge Booster Training Bytes - Virtuoso Visualization and Analysis XL

Udit Rajput

This blog describes how to efficiently use Virtuoso Visualization and Analysis XL.
- 10 Aug 2022

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