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Breakfast Bytes: Photonics Keynote: Transitioning from Electrical to Optical I/O

Paul McLellan

At last year's Photonics Summit, actually held earlier this year due to technical issues when the videos were meant to go live, the keynote was given by James Jaussi, Senior Principal Engineer and Director of the PHY Research Lab in Intel La...
- 19 May 2022
カスタムIC／ミックスシグナル: Spectre Tech Tips: Spectre Strobe機能の使用

Custom IC Japan

Spectre®回路シミュレータをご利用のお客様で、SpectreのStrobe機能で対応可能な用途にmaxstep機能を使用しているケースが時々見受けられます。そこでこのブログでは、SpectreのStrobe機能の使い方を中心に説明します。 Virtuoso® Visualization and Analysis XL (ViVA XL)やOCEANなどのツールで波形のポストプロセスを行う目的でSpectreシミュレーションを実行し、このポストプロセスを等間隔で行う...
- 18 May 2022
Academic Network: Organic Printed Electronics PDK Education Kit Available Now

Anton Klotz

The Virtuoso Education Kit has just been released and now there is already a new kit available: The Organic Printed Electronics PDK Education Kit! This kit also uses Virtuoso as the main Cadence tool, allowing schematic creation, layouting, and paras...
- 18 May 2022
Computational Fluid Dynamics: Lunch & Learn and Women in Engineering at the ASME Turbo Expo 2022

Veena Parthan

Cadence is looking forward to meeting with you at the 'Lunch and Learn' and 'Women in Engineering' sessions at ASME Turbomachinery Expo 2022. Seats are limited! Register today to ensure your spot.
- 18 May 2022
Breakfast Bytes: Arm SystemReady Compliance Using Emulation

Paul McLellan

Yesterday in my post Cadence and Arm I wrote about how Cadence has worked with Arm over the last decade or more. Well, it is Arm again today since there is an Arm event at which Cadence is giving one of the presentations. Today is the second day...
- 18 May 2022
System, PCB, & Package Design : ASCENT: Training Insights: Get Rid of Design Errors in Allegro System Capture

Supriya Srivastava

With thousands of components connected across a multi-layered board, anticipating the complexity of your layout design at the logic design stage can be quite a challenge. For example, how to ensure that the logical design you are trying to create fun...
- 18 May 2022
Analog/Custom Design: Virtuoso Meets Maxwell: Improving Manufacturability and Yield

Parula

This blog is to announce the official release of the Fillet capability. The Fillet capability is another remarkable addition to our existing Virtuoso RF features portfolio. For analog and high-speed circuits, or areas of a design where shock and vibration to the design might disrupt connections, adding fillets to your design is probably the solution to improve yield and manufacturability.
- 17 May 2022
Breakfast Bytes: Cadence and Arm

Paul McLellan

I've been working with Arm for longer than Cadence has. In fact, I was working with Arm before it was Arm, back when the Arm 1 was a processor developed by Acorn Computers (the A in Arm originally stood for Acorn). I described my early involveme...
- 17 May 2022
Computational Fluid Dynamics: Less than a Minute to Water-tight Geometry Using Fidelity CFD AutoSeal

Veena Parthan

Cadence Fidelity CFD offers AutoSeal technology, a geometry clean-up tool for faster results for multiple design tests, reducing the time to meshing towards an efficient design process.
- 16 May 2022
System, PCB, & Package Design : Frequency Matters Podcast: System Analysis Solutions

Sherry Hess

By Sherry Hess Recently I posted a blog on LinkedIn called "High Tech Everything" and it caught the attention of Microwave Journal. As such, it have spawn a similar podcast on how Cadence is expanding into multiple verticals with system analysis solutions...
- 16 May 2022
Breakfast Bytes: The 2022 Kaufman Dinner

Paul McLellan

On May 12th, it was the Kaufman Award Ceremony and Banquet at which Cadence's CEO Anirudh Devgan was awarded the 2021 Phil Kaufman Award. Yes, I know it is 2022. Normally the award dinner is held late in the year, but for Covid-reasons, it was postpo...
- 16 May 2022
Breakfast Bytes: Sunday Brunch Video for 15th May 2022

Paul McLellan

https://youtu.be/F-dN8wy-iNc Made at Steve Brown's "moving to San Diego party" (camera Larry Lapides) Monday: no post Tuesday: TechInsights: Foundation for the Future Wednesday: Open RAN Phase 2 Thursday: What Is High-NA EUV? Friday: N...
- 15 May 2022
Academic Network: Searching on Cadence Support Is Now Even Easier!

Kira Jones

The Cadence Learning and Support Portal is useful to academia in many ways: Online Training, Rapid Adoption Kits (RAKs), Generic Process Design Kits (GPDKs), troubleshooting database, and so much more. But with so many benefits, it is helpful to be a...
- 13 May 2022
Breakfast Bytes: New Book: Hyperscale Computing Trends 2022

Paul McLellan

Cadence has a new book out. Written by Frank Schirrmeister and myself, it is called Hyperscale Computing Trends: 2022 Outlook. In some ways, it is similar to the Year of Breakfasts books that I have done each year for the last few years, a sort of be...
- 13 May 2022
Verification: Demystifying CXL.cache

Sangeeta Soni

If you have worked with Peripheral Component Interconnect Express (PCIe) in the past, you might have heard Compute Link Express (CXL) is break-through technology for modern day compute requirements driven by high-performance computing, cloud, AI and ML. Of course, CXL buzz is for real and is well resonating with big industry players in processing and storage landscape. We are already seeing pre-production CXL design demos…
- 13 May 2022
System, PCB, & Package Design : IC Packagers: Three Reasons for Allegro Package Designer Plus Users to Move to OrCAD/Allegro 17.4 (SPB174) - HotFix028 Release

Sanjiv Bhatia

The HotFix 028 of our 17.4-2019 release was rolled out at the end of March and is now available for download and installation. The release brings critical bug fixes, product enhancements, and new features. Let’s talk about some of the exciting...
- 13 May 2022
Breakfast Bytes: What Is High-NA EUV?

Paul McLellan

I'm sure you know that the lowest levels of ICs fabricated at the most advanced nodes, basically anything at 5nm and below, use EUV lithography (extreme ultraviolet). You probably also know that only one company in the world, ASML in the Netherla...
- 12 May 2022
Computational Fluid Dynamics: CadenceLIVE Silicon Valley 2022 - CFD Track: Seven Reasons to Attend

AnneMarie CFD

On June 8th and 9th, it is CadenceLIVE Americas. It is planned to be in-person at the Santa Clara Convention Center in Silicon Valley and that is already your first important reason to join us! We are finally getting back to face-to-face networking, enjoying wonderful food and drinks, and seizing invaluable opportunities to discuss, learn and share ideas and opinions with colleagues, peers, industry thought leaders and…
- 12 May 2022
Breakfast Bytes: Open RAN Phase 2

Paul McLellan

I first wrote about Open RAN in my post Fourth 4G Network Goes Live in Japan. Open RAN is a program driven by a group of European operators to build specifications for common architecture instead of getting "locked into" the closed architec...
- 11 May 2022
Verification: Renesas Leverages Palladium + System VIP Solution for System Verification and Performance Optimization

Vinod Khera

Verifying bus performance by analyzing bandwidth and latency over time in chips is tricky. Renesas in collaboration with Cadence used a comprehensive emulation package and designed a new efficient bus performance verification scheme that helped them to witness a stellar performance with 160x speedup in actual simulation or emulation itself along with 16x speed up in bandwidth and latency calculation and extracting the…
- 10 May 2022
Digital Design: Power Is HOT and Touches Everything and Everybody! But the Challenge Is To Deal With Low Power During Design Synthesis; How?

Neha Joshi
Low-Power synthesis is one of the important stages in the full IC flow. Here, you synthesize the design from behavioral description to gates while optimizing for dynamic and leakage power using various techniques. We understand that it is not always easy to estimate power, but Cadence offers a solution in the form of a low-power synthesis flow with Genus.

Are you interested in exploring:

What the complete low-power synthesis…
- 10 May 2022
PCB、IC封装：设计与仿真分析: Clarity 3D Solver 2022版本闪亮登场

Sigrity

最新的电磁设计同步分析功能有助于提高 IC、IC 封装和高性能 PCB 设计的速度美国加州圣何塞(DesignCon)—楷登电子（Cadence Design Systems, Inc.）在近期结束的 DesignCon 2022 展会上发布了用于 IC、IC 封装和高性能 PCB 设计电磁 (EM) 设计中同步分析的 Cadence® Clarity 3D Solver 最新版本。该版本的新功能和工作流程包括：新的分布式网格划分功能，可提供至少 10 倍性...
- 10 May 2022
Breakfast Bytes: TechInsights: Foundation for the Future

Paul McLellan

The second day of the Linley Spring Processor Conference opened with a keynote by Jason Abt, the Chief Technology Officer of TechInsights, titled Foundations for the Future. There's a good chance you don't know who TechInsights is. Well, firs...
- 10 May 2022
PCB設計／ICパッケージ設計: ASCENT: デザインのコンストレイントを簡単な方法で設定する

SPB Japan

コンストレイント(制約条件)は、PCB デザインの要件が論理的、物理的の両方の観点で満たされることを保証するためのルールです。コンストレイントは、パーツ、ピン、ネットなどの様々なオブジェクトに定義できます。このブログでは、電気的ネットに定義されるコンストレイントに焦点を当てます。これらのコンストレイントには、スタブの長さや伝搬遅延("Propagation Delay")といった電気的なものと、ラインの最小幅やスタティックでのフェーズ公差といった物理的なものとがあります。設計...
- 9 May 2022
PCB、IC封装：设计与仿真分析: 汽车行业合规与功能安全指南：ISO 26262 标准出台十周年

SDA China

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“Happy 10th Birthday ISO 26262”。 space 汽车行业的“双十一” 去年11月11日是 ISO 26262 标准发布 10 周年纪念日，该标准于 2011 年 11 月 11 日首次发布，全称是《道路车辆功能安全》。这是一项有关汽车电气和（或）电子（E/E）系统功能安全的国际标准。该标...
- 9 May 2022

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