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I joined Cadence in July 2000 and was immediately put on a three-month training to learn and understand the simulator tools. There were formal training sessions, and I had a mentor whom I could ask all my queries. But most of the time, I was on my own, as "learning by doing" was the motto of my mentor. Today, after completing 20 years at Cadence, I can tell you that it works great, especially in cases where the tool is…

With advanced-process nodes, the physical delay of a standard cell, net delay, and congestion all lead to a higher requirement on the netlist. Genus/Innovus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optimization. This gives great power, performance, and area (PPA) results in complex SoC designs while maintaining quality and design schedule.

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