Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Digital Design: Library Characterization Tidbits: Basics of Standard Cell Characterization and More

AbhaRawat

Characterization of standard cell libraries using the Liberate Characterization solution is broadly divided into five stages. Read this blog to know about the related basics and the step-by-step procedure.
- 20 Nov 2019
Breakfast Bytes: 2nd WOSET Workshop on Open-Source EDA

Paul McLellan

During ICCAD earlier in the month, there was the 2nd WOSET, which stands for Workshop on Open-Source EDA Technology. I wasn't there but Anton Klotz, who runs the Cadence Academic Network in Europe, was there and this is based on his report. I wro...
- 20 Nov 2019
System, PCB, & Package Design : IC Packagers: A Cross-Section of Changes

Tyler

While 17.4 has only been amongst you for a month, now, I’ve had a few questions regarding manipulating your layer stack-up in the new release. We covered scripting changes previously, but a quick chat about the general use model is warranted. T...
- 19 Nov 2019
System, PCB, & Package Design : BoardSurfers: Power of Information – Quickly Getting Started with Allegro and OrCAD Release 17.4-2019

Jasmine

The Allegro and OrCAD 7.4 release is now available for download and installation. Many of you must have already started using it and many more of you must be planning to install it in the coming days or weeks. Do you have all it needs to use the programs?
- 19 Nov 2019
Breakfast Bytes: Verifying Processor Security, Part 2

Paul McLellan

This is the second post about Eli Singerman's keynote at the recent Jasper User Group. The first was Formally Verifying Processor Security. In the last couple of years, high-performance processors (not just Intel's) have been shown to be...
- 19 Nov 2019
Analog/Custom Design: Virtuoso Meets Maxwell: Package PDK in Virtuoso! How Is It Even Possible? (Part 2)

VRF Knight

Alright… I’m back again to amuse you with another part on how to set up Package PDK in Virtuoso. I hope you enjoyed what I introduced to you in the previous part and I hope you are applying what you have learned in your design flow on daily bases.
- 18 Nov 2019
Breakfast Bytes: Formally Verifying Processor Security

Paul McLellan

Intel has had a couple of major events that totally changed their attitude to verification. The first was in 1994 when they had the Pentium floating-point divide bug and management said “don’t ever let this happen again”. In 1996, t...
- 18 Nov 2019
PCB、IC封装：设计与仿真分析: RF设计直播课程：如何提高RF前端模块封装设计的迭代效率

SDA China

大家好，我是Principal Customer Engagement Engineer江亮，从事射频前端模块设计七年，先后受聘于Qorvo，RDA等多家射频半导体研发企业。熟悉射频前端模块设计的全流程，拥有丰富的射频模块设计经验，曾主导、参与设计了多款产品，包括功率放大器，天线开关，低噪声放大器，耦合器等前端模块电路，并投产取得商业成功。众所周知，随着5G的商业化演进，射频前端模块的设计越来越复杂，越来越多的不同工艺的裸片将集成到一个封装模块中，集成化小型化的需求导致设计的流程越来越复杂，并...
- 15 Nov 2019
Academic Network: CADathlon at ICCAD 2019

Anton Klotz

Last week, I visited the Cadathlon@ICCAD event at the 2019 International Conference on Computer Aided Design . It was my first CADathlon and I was quite intrigued, since the organizers webpage announced it boldly as the “Olympic Games...
- 15 Nov 2019
System, PCB, & Package Design : BoardSurfers: What's Happening Around 17.4-2019?

mrigashira

Allegro and OrCAD 17.4-2019 was released on October 18 and we have since then been getting a lot of queries about a lot of things. How do I install the products? What are the system requirements? What has changed? What's there in it for me? Is there ...
- 15 Nov 2019
Breakfast Bytes: OpenROAD: Open-Source EDA from RTL to GDSII

Paul McLellan

OpenROAD is a DARPA program to attempt to build a no-human-in-the-loop EDA flow, using only open-source software. The goal is to go from RTL to GDSII fully automatically. In a leading-edge process node. With zero DRC errors. In less than 24 hour...
- 15 Nov 2019
Academic Network: Successful Speaker Event—Engaging with Professor in Shanghai

Tracy Zhu

The Cadence Academic Network hosted an Academic Speaker Series event, in collaboration with the Shanghai Site Technical Talk series, in Cadence Shanghai Office. The talk attracted more than 150 Cadence employees! I organized ...
- 14 Nov 2019
Breakfast Bytes: What Does P≠NP Mean?

Paul McLellan

Recently I wrote about computational software and said that EDA algorithms are all "intractable". That was in the post Computational Software. What does intractable mean? If you know anything about algorithms, you might have heard term...
- 14 Nov 2019
Analog/Custom Design: Virtuosity: Usability Enhancements in the Property Editor

KomalJohar

Goes without saying that the Property Editor is the most frequently used feature of the Virtuoso platform. If you haven’t yet noticed the usability enhancements in the Property Editor, read ahead to know about a few usability enhancements that we have provided in the Property Editor.
- 14 Nov 2019
Breakfast Bytes: Die-to-Die Interconnect: The UltraLink D2D PHY IP

Paul McLellan

One of the big trends that has been happening somewhat below the radar is the growth of various forms of 3D packaging. I noted this at HOT CHIPS in summer, when a big percentage of the designs were not a single big die, but were multiple die in the s...
- 13 Nov 2019
System, PCB, & Package Design : IC Packagers: Plan Your Escape with Modernized Structures

Tyler

Many of you, our regular readers, are familiar with via structures. These reusable patterns of vias, clines, shape, and keep-out shapes, and return path elements allow you to escape a single pin then replicate that structure (or pattern of structures...
- 12 Nov 2019
Life at Cadence: Asking Our Employees: What Makes Us Great in Europe?

Eduardos

As the project manager of our global Great Place to Work programs, I’ve had the opportunity to attend the annual Great Place to Work Conference in Greece and Sweden where they’ve announced their top workplaces in Europe the past couple ye...
- 12 Nov 2019
Analog/Custom Design: Virtuoso Meets Maxwell: Help With Electromagnetic Analysis - Part III

Kabir

This is the third blog in the multi-part series that aims at providing in-depth details of electromagnetic analysis in the Virtuoso RF solution. To know about the benefits of preprocessing of layout shapes for electromagnetic analysis, read
- 11 Nov 2019
System, PCB, & Package Design : What's in a Name? From Allegro EDM to Pulse in 17.4-2019

Auromala

Allegro EDM (Engineering Data Management) 17.4-2019 is out! So, what's in it for you?
- 11 Nov 2019
Breakfast Bytes: The 2019 Jasper User Group

Paul McLellan

Last week was the Jasper User Group meeting, the biggest annual gathering of formal verification engineers. This is the 13th meeting. Ziyad recalled the first, held at the TechMart, to which about 15 people attended. This year was the sixth since Cad...
- 11 Nov 2019
Academic Network: Exciting Academic News on OrCAD

Anton Klotz

There’s some exciting news about the Cadence OrCAD® Software, especially for academics! Generations of analog designers have used Cadence ® PSpice® Simulator, which is a part of the OrCAD package, as their first analog simulator. Now...
- 9 Nov 2019
PCB、IC封装：设计与仿真分析: 隐藏在PCB设计中的七个DFM问题

TeamAllegro

本文由Cadence的北美经销商EMA Design Automation撰写。 space 当我们完成设计并将其送到制造厂后，如果我们的产品存在大量可制造性设计（DFM）错误，那么便会造成产品搁置。这种情况不仅令人沮丧，而且代价高昂。在项目早期尽早考虑制造问题有助于降低成本、缩短开发时间，并确保设计顺利过渡到生产阶段。相反，若不这样做，便会造成不良后果。凭借多年的行业经验，我们总结了7大妨碍PCB可制造性的主要DFM问题。虽然以下列出的部分内容是设计方面的最佳实践，但还有一些是由制作/制造...
- 8 Nov 2019
Breakfast Bytes: OpenTitan: Secure Boot with a Silicon Root of Trust

Paul McLellan

At HOTCHIPS last year, Google presented its security processor Titan. You can read lots of details at my post Google's Titan: How They Stop You Slipping a Bogus Server into Their Datacenter. Titan provides a silicon root of trust (RoT) ...
- 8 Nov 2019
Digital Design: Library Characterization Tidbits: Reasons to Start Following This New Blog Series

AbhaRawat

Library Characterization Tidbits is a blog series aimed at providing insight into the useful software and documentation enhancements in the LIBERATE release.
- 7 Nov 2019
Breakfast Bytes: Computational Software

Paul McLellan

This is the third post in a series on computation in EDA and adjacent markets. The previous two were Computation and the Data Explosion and Computational Hardware. All EDA algorithms are computationally intractable, in that it is impossible to ...
- 7 Nov 2019

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.