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Verification: Demystifying CXL.cache

Sangeeta Soni

If you have worked with Peripheral Component Interconnect Express (PCIe) in the past, you might have heard Compute Link Express (CXL) is break-through technology for modern day compute requirements driven by high-performance computing, cloud, AI and ML. Of course, CXL buzz is for real and is well resonating with big industry players in processing and storage landscape. We are already seeing pre-production CXL design demos…
- 13 May 2022
System, PCB, & Package Design : IC Packagers: Three Reasons for Allegro Package Designer Plus Users to Move to OrCAD/Allegro 17.4 (SPB174) - HotFix028 Release

Sanjiv Bhatia

The HotFix 028 of our 17.4-2019 release was rolled out at the end of March and is now available for download and installation. The release brings critical bug fixes, product enhancements, and new features. Let’s talk about some of the exciting...
- 13 May 2022
Breakfast Bytes: What Is High-NA EUV?

Paul McLellan

I'm sure you know that the lowest levels of ICs fabricated at the most advanced nodes, basically anything at 5nm and below, use EUV lithography (extreme ultraviolet). You probably also know that only one company in the world, ASML in the Netherla...
- 12 May 2022
Computational Fluid Dynamics: CadenceLIVE Silicon Valley 2022 - CFD Track: Seven Reasons to Attend

AnneMarie CFD

On June 8th and 9th, it is CadenceLIVE Americas. It is planned to be in-person at the Santa Clara Convention Center in Silicon Valley and that is already your first important reason to join us! We are finally getting back to face-to-face networking, enjoying wonderful food and drinks, and seizing invaluable opportunities to discuss, learn and share ideas and opinions with colleagues, peers, industry thought leaders and…
- 12 May 2022
Breakfast Bytes: Open RAN Phase 2

Paul McLellan

I first wrote about Open RAN in my post Fourth 4G Network Goes Live in Japan. Open RAN is a program driven by a group of European operators to build specifications for common architecture instead of getting "locked into" the closed architec...
- 11 May 2022
Verification: Renesas Leverages Palladium + System VIP Solution for System Verification and Performance Optimization

Vinod Khera

Verifying bus performance by analyzing bandwidth and latency over time in chips is tricky. Renesas in collaboration with Cadence used a comprehensive emulation package and designed a new efficient bus performance verification scheme that helped them to witness a stellar performance with 160x speedup in actual simulation or emulation itself along with 16x speed up in bandwidth and latency calculation and extracting the…
- 10 May 2022
Digital Design: Power Is HOT and Touches Everything and Everybody! But the Challenge Is To Deal With Low Power During Design Synthesis; How?

Neha Joshi
Low-Power synthesis is one of the important stages in the full IC flow. Here, you synthesize the design from behavioral description to gates while optimizing for dynamic and leakage power using various techniques. We understand that it is not always easy to estimate power, but Cadence offers a solution in the form of a low-power synthesis flow with Genus.

Are you interested in exploring:

What the complete low-power synthesis…
- 10 May 2022
PCB、IC封装：设计与仿真分析: Clarity 3D Solver 2022版本闪亮登场

Sigrity

最新的电磁设计同步分析功能有助于提高 IC、IC 封装和高性能 PCB 设计的速度美国加州圣何塞(DesignCon)—楷登电子（Cadence Design Systems, Inc.）在近期结束的 DesignCon 2022 展会上发布了用于 IC、IC 封装和高性能 PCB 设计电磁 (EM) 设计中同步分析的 Cadence® Clarity 3D Solver 最新版本。该版本的新功能和工作流程包括：新的分布式网格划分功能，可提供至少 10 倍性...
- 10 May 2022
Breakfast Bytes: TechInsights: Foundation for the Future

Paul McLellan

The second day of the Linley Spring Processor Conference opened with a keynote by Jason Abt, the Chief Technology Officer of TechInsights, titled Foundations for the Future. There's a good chance you don't know who TechInsights is. Well, firs...
- 10 May 2022
PCB設計／ICパッケージ設計: ASCENT: デザインのコンストレイントを簡単な方法で設定する

SPB Japan

コンストレイント(制約条件)は、PCB デザインの要件が論理的、物理的の両方の観点で満たされることを保証するためのルールです。コンストレイントは、パーツ、ピン、ネットなどの様々なオブジェクトに定義できます。このブログでは、電気的ネットに定義されるコンストレイントに焦点を当てます。これらのコンストレイントには、スタブの長さや伝搬遅延("Propagation Delay")といった電気的なものと、ラインの最小幅やスタティックでのフェーズ公差といった物理的なものとがあります。設計...
- 9 May 2022
PCB、IC封装：设计与仿真分析: 汽车行业合规与功能安全指南：ISO 26262 标准出台十周年

SDA China

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“Happy 10th Birthday ISO 26262”。 space 汽车行业的“双十一” 去年11月11日是 ISO 26262 标准发布 10 周年纪念日，该标准于 2011 年 11 月 11 日首次发布，全称是《道路车辆功能安全》。这是一项有关汽车电气和（或）电子（E/E）系统功能安全的国际标准。该标...
- 9 May 2022
Digital Design: Are You Planning To Synthesize Your Design? Do You Want To Explore the Synthesis Flow in Genus Synthesis Solution?

Neha Joshi

A Logic Synthesis is a process of optimizing the design's area, timing, and power.

You might be a beginner in the synthesis world, but we can help you sail through it smoothly. It's time to introduce yourself to our tool for synthesis, Genus Synthesis Solution.

The ultimate goal of the Cadence^® Genus Synthesis Solution is very simple: deliver the best possible productivity during register-transfer-level (RTL…
- 9 May 2022
Breakfast Bytes: Linley: Western Digital's RISC-V Strategy

Paul McLellan

Western Digital acquired SanDisk in 2016. In 2017, Martin Fink, then the CTO of Western Digital, announced that it would convert all the cores used on its devices to RISC-V. This was one of the first solid commitments to RISC-V in a commercial s...
- 9 May 2022
PCB設計／ICパッケージ設計: BoardSurfers: IPC-2581の利用によるレイヤースタックアップデータの受け渡し

SPB Japan

設計意図やスタックアップ情報を設計の初期段階のうちに製造部門や製造委託先と共有しておけば、製品設計に影響を与え製品納入を遅らせてしまうような製造やアセンブリ関連の問題を回避することができます。しかし、製造データをやり取りするための標準的なコミュニケーション手段を持たない場合、レビューサイクルの中で情報が誤って解釈されたり、完全に失われたりする可能性があります。また、手作業で作成されたデータは統一性に欠け、必要なパラメータが不足している可能性もあります。もしも設計側と製造側の双方がIPC-2581...
- 8 May 2022
Breakfast Bytes: Sunday Brunch Video for 8th May 2022

Paul McLellan

https://youtu.be/xADMKcqKLNg Made on Communication Hill with Sheep (camera Carey) Monday: Gabrièle Saucier on the History of IP Tuesday: ESD Alliance CEO Outlook 2022 Wednesday: Always On at D&R Thursday: A History of Cadence in the C...
- 8 May 2022
Digital Design: Chris, Kris, Cris, Your Name, My Name; Does How You Spell the Name Matter to Conformal?

FormerMember

No matter how your name is spelt in different countries, and how they say it, once they get to know you, people identify you as the same person.

Ah! this is Chris, Cris, Kris, Kirshner, or Krishna. And I know this dude, even though he has transformed since I last saw him, and is 10 years older than what I remember.

Likewise, different tools have different ways of naming the same design object and the default rules rarely…
- 7 May 2022
PCB、IC封装：设计与仿真分析: 如何建立一个数据中心：全靠 SerDes和散热

SDA China

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“How to Build a Data Center: It's All About the SerDes...and Thermal”。 space 我们可能不需要建立一个数据中心，但很可能会参与设计用于数据中心的芯片；或者在关注数据中心的 IP；或者担心先进节点设计工具的某些方面，其中大部分会发生在数据中心。因此，很有必要简单...
- 6 May 2022
Digital Design: Do You Want to Explore Instances in Genus Synthesis Solution Layout GUI?

Neha Joshi

What comes to your mind when we say Genus Layout GUI (Graphical User Interface)? You picture the floorplan filled with instances and objects. Imagine you need to highlight the specific instance or timing path in GUI?

Do you think it’s tricky? Not at all!!

Genus Synthesis Solution GUI (Graphical User Interface) helps you view and highlight the instances and timing results to better explore/debug your design.

Now think…
- 6 May 2022
Breakfast Bytes: An Interview with Morris Chang

Paul McLellan

A couple of weeks ago, Morris Chang, the founder of TSMC and, for a long time (twice), its CEO, was interviewed at the Brookings Institution and the Center for Strategic and International Studies (CSIS), two think tanks in Washington DC. Th...
- 6 May 2022
System, PCB, & Package Design : ASCENT: Reasons to Move to 17.4-2019 HotFix SPB17.40.028 of Allegro Pulse

Auromala

HotFix SPB17.40.028 of 17.4-2019 of Allegro® Pulse is out and is available for download. This release includes various enhancements, new features, and product changes that address design challenges. Let’s look at some of the Alle...
- 6 May 2022
PCB、IC封装：设计与仿真分析: AWR：智能射频设计

SDA China

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“AWR: Intelligent RF Design”。 space 今年AWR Design Environment® 推出的新版本V16具有跨平台的工作流程，支持基于 Virtuoso®（芯片）和 Allegro®（PCB/封装）平台的射频到毫米波设计，并与系统级分析解决方案 Clarity 3D Solve...
- 5 May 2022
Breakfast Bytes: A History of Cadence in the Cloud

Paul McLellan

Cadence Cloud started before there even was a cloud. We just didn't call it Cadence Cloud. Back in the early 2000s, when I was on my first tour of duty at Cadence, we created something that we called Virtual CAD, or VCAD for short. The idea was that ...
- 5 May 2022
Verification: Enflame Accelerates the DFT and DFD Verification using Palladium

Vinod Khera

DFT (Design for Testability) provides the much-needed support to the manufacturers to catch up with the increasing demand and pressure for mass production. It helps produce chips with flawless design and perfect quality for challenging applications. ...
- 5 May 2022
System, PCB, & Package Design : This Month in IDA

Sherry Hess

This month the In-Design Analysis (IDA) team kicked off its new blog program with an insightful look at "High-Tech Everything” from group director Sherry Hess and advice from our Celsius expert Melika Roshandell on "Finding and fixing thermal issues early in the PCB design flow."
- 4 May 2022
PCB、IC封装：设计与仿真分析: OMNIS – 如何在汽车领域应对当今和未来的多物理场仿真挑战？

SDA China

本文作者：Yannick Baux, Cadence产品研发总监 space 汽车行业一直使用 CFD 工具来设计和优化车辆的各个方面，从外部空气动力学到降噪，再到热管理、内部燃烧等等。大多数情况下，在设计过程中，所有上述内容被结合在一起，称为虚拟原型，以便将车辆作为一个系统进行优化。然而，各种应用背后的物理原理往往大不相同，这就意味着需要为每个特定的应用采用专门的技术。因此，设计师、科学家或工程师经常使用大量不同的 CAE 代码和软件工具，这些工具都有不同的界面（GUI）、数据设置、...
- 4 May 2022

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